svn commit: r327392 - in head/sys: arm/altera/socfpga arm/rockchip arm/samsung/exynos dev/mmc/host
Emmanuel Vadot
manu at FreeBSD.org
Sat Dec 30 22:01:19 UTC 2017
Author: manu
Date: Sat Dec 30 22:01:17 2017
New Revision: 327392
URL: https://svnweb.freebsd.org/changeset/base/327392
Log:
dwmmc: Fully subclass driver
Fully subclass the dwmmc driver and split every driver into multiple files.
There is still a few quirks in the dwmmc driver that will need some work.
Tested On: Pine64 Rock64
Differential Revision: https://reviews.freebsd.org/D13615
Added:
head/sys/dev/mmc/host/dwmmc_altera.c
- copied, changed from r327391, head/sys/dev/mmc/host/dwmmc_hisi.c
head/sys/dev/mmc/host/dwmmc_rockchip.c
- copied, changed from r327391, head/sys/dev/mmc/host/dwmmc_hisi.c
head/sys/dev/mmc/host/dwmmc_samsung.c (contents, props changed)
Modified:
head/sys/arm/altera/socfpga/files.socfpga
head/sys/arm/rockchip/files.rk30xx
head/sys/arm/samsung/exynos/files.exynos5
head/sys/dev/mmc/host/dwmmc.c
head/sys/dev/mmc/host/dwmmc_hisi.c
head/sys/dev/mmc/host/dwmmc_var.h
Modified: head/sys/arm/altera/socfpga/files.socfpga
==============================================================================
--- head/sys/arm/altera/socfpga/files.socfpga Sat Dec 30 20:28:29 2017 (r327391)
+++ head/sys/arm/altera/socfpga/files.socfpga Sat Dec 30 22:01:17 2017 (r327392)
@@ -10,6 +10,7 @@ arm/altera/socfpga/socfpga_mp.c optional smp
arm/altera/socfpga/socfpga_gpio.c optional gpio
dev/mmc/host/dwmmc.c optional dwmmc
+dev/mmc/host/dwmmc_altera.c optional dwmmc
# Arria 10
arm/altera/socfpga/socfpga_a10_manager.c standard
Modified: head/sys/arm/rockchip/files.rk30xx
==============================================================================
--- head/sys/arm/rockchip/files.rk30xx Sat Dec 30 20:28:29 2017 (r327391)
+++ head/sys/arm/rockchip/files.rk30xx Sat Dec 30 22:01:17 2017 (r327392)
@@ -9,3 +9,4 @@ arm/rockchip/rk30xx_gpio.c optional gpio
arm/rockchip/rk30xx_mp.c optional smp
dev/mmc/host/dwmmc.c optional dwmmc
+dev/mmc/host/dwmmc_rockchip.c optional dwmmc
Modified: head/sys/arm/samsung/exynos/files.exynos5
==============================================================================
--- head/sys/arm/samsung/exynos/files.exynos5 Sat Dec 30 20:28:29 2017 (r327391)
+++ head/sys/arm/samsung/exynos/files.exynos5 Sat Dec 30 22:01:17 2017 (r327392)
@@ -22,3 +22,4 @@ arm/samsung/exynos/chrome_ec_spi.c optional chrome_ec
arm/samsung/exynos/chrome_kb.c optional chrome_kb
dev/mmc/host/dwmmc.c optional dwmmc
+dev/mmc/host/dwmmc_samsung.c optional dwmmc
Modified: head/sys/dev/mmc/host/dwmmc.c
==============================================================================
--- head/sys/dev/mmc/host/dwmmc.c Sat Dec 30 20:28:29 2017 (r327391)
+++ head/sys/dev/mmc/host/dwmmc.c Sat Dec 30 22:01:17 2017 (r327392)
@@ -131,13 +131,6 @@ static struct resource_spec dwmmc_spec[] = {
#define HWTYPE_MASK (0x0000ffff)
#define HWFLAG_MASK (0xffff << 16)
-static struct ofw_compat_data compat_data[] = {
- {"altr,socfpga-dw-mshc", HWTYPE_ALTERA},
- {"samsung,exynos5420-dw-mshc", HWTYPE_EXYNOS},
- {"rockchip,rk2928-dw-mshc", HWTYPE_ROCKCHIP},
- {NULL, HWTYPE_NONE},
-};
-
static void
dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
@@ -448,52 +441,9 @@ parse_fdt(struct dwmmc_softc *sc)
sc->bus_hz = dts_value[0];
}
- /*
- * Platform-specific stuff
- * XXX: Move to separate file
- */
-
- if ((sc->hwtype & HWTYPE_MASK) != HWTYPE_EXYNOS)
- return (0);
-
- if ((len = OF_getproplen(node, "samsung,dw-mshc-ciu-div")) <= 0)
- return (ENXIO);
- OF_getencprop(node, "samsung,dw-mshc-ciu-div", dts_value, len);
- sc->sdr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT);
- sc->ddr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT);
-
- if ((len = OF_getproplen(node, "samsung,dw-mshc-sdr-timing")) <= 0)
- return (ENXIO);
- OF_getencprop(node, "samsung,dw-mshc-sdr-timing", dts_value, len);
- sc->sdr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) |
- (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT));
-
- if ((len = OF_getproplen(node, "samsung,dw-mshc-ddr-timing")) <= 0)
- return (ENXIO);
- OF_getencprop(node, "samsung,dw-mshc-ddr-timing", dts_value, len);
- sc->ddr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) |
- (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT));
-
return (0);
}
-static int
-dwmmc_probe(device_t dev)
-{
- uintptr_t hwtype;
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
- if (hwtype == HWTYPE_NONE)
- return (ENXIO);
-
- device_set_desc(dev, "Synopsys DesignWare Mobile "
- "Storage Host Controller");
- return (BUS_PROBE_DEFAULT);
-}
-
int
dwmmc_attach(device_t dev)
{
@@ -504,10 +454,6 @@ dwmmc_attach(device_t dev)
sc = device_get_softc(dev);
sc->dev = dev;
- if (sc->hwtype == HWTYPE_NONE) {
- sc->hwtype =
- ofw_bus_search_compatible(dev, compat_data)->ocd_data;
- }
/* Why not to use Auto Stop? It save a hundred of irq per second */
sc->use_auto_stop = 1;
@@ -539,19 +485,6 @@ dwmmc_attach(device_t dev)
if (sc->desc_count == 0)
sc->desc_count = DESC_MAX;
- if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_ROCKCHIP) {
- sc->use_pio = 1;
- sc->pwren_inverted = 1;
- } else if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) {
- WRITE4(sc, EMMCP_MPSBEGIN0, 0);
- WRITE4(sc, EMMCP_SEND0, 0);
- WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |
- MPSCTRL_SECURE_WRITE_BIT |
- MPSCTRL_NON_SECURE_READ_BIT |
- MPSCTRL_NON_SECURE_WRITE_BIT |
- MPSCTRL_VALID));
- }
-
/* XXX: we support operation for slot index 0 only */
slot = 0;
if (sc->pwren_inverted) {
@@ -1154,9 +1087,6 @@ dwmmc_write_ivar(device_t bus, device_t child, int whi
}
static device_method_t dwmmc_methods[] = {
- DEVMETHOD(device_probe, dwmmc_probe),
- DEVMETHOD(device_attach, dwmmc_attach),
-
/* Bus interface */
DEVMETHOD(bus_read_ivar, dwmmc_read_ivar),
DEVMETHOD(bus_write_ivar, dwmmc_write_ivar),
@@ -1171,16 +1101,5 @@ static device_method_t dwmmc_methods[] = {
DEVMETHOD_END
};
-driver_t dwmmc_driver = {
- "dwmmc",
- dwmmc_methods,
- sizeof(struct dwmmc_softc),
-};
-
-static devclass_t dwmmc_devclass;
-
-DRIVER_MODULE(dwmmc, simplebus, dwmmc_driver, dwmmc_devclass, NULL, NULL);
-DRIVER_MODULE(dwmmc, ofwbus, dwmmc_driver, dwmmc_devclass, NULL, NULL);
-#ifndef MMCCAM
-MMC_DECLARE_BRIDGE(dwmmc);
-#endif
+DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods,
+ sizeof(struct dwmmc_softc));
Copied and modified: head/sys/dev/mmc/host/dwmmc_altera.c (from r327391, head/sys/dev/mmc/host/dwmmc_hisi.c)
==============================================================================
--- head/sys/dev/mmc/host/dwmmc_hisi.c Sat Dec 30 20:28:29 2017 (r327391, copy source)
+++ head/sys/dev/mmc/host/dwmmc_altera.c Sat Dec 30 22:01:17 2017 (r327392)
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Andrew Turner.
+ * Copyright 2017 Emmanuel Vadot <manu at freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,56 +41,55 @@ __FBSDID("$FreeBSD$");
#include <dev/mmc/host/dwmmc_var.h>
-static device_probe_t hisi_dwmmc_probe;
-static device_attach_t hisi_dwmmc_attach;
+static struct ofw_compat_data compat_data[] = {
+ {"altr,socfpga-dw-mshc", 1},
+ {NULL, 0},
+};
static int
-hisi_dwmmc_probe(device_t dev)
+altera_dwmmc_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (!ofw_bus_is_compatible(dev, "hisilicon,hi6220-dw-mshc"))
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "Synopsys DesignWare Mobile "
- "Storage Host Controller (HiSilicon)");
+ "Storage Host Controller (Altera)");
return (BUS_PROBE_VENDOR);
}
static int
-hisi_dwmmc_attach(device_t dev)
+altera_dwmmc_attach(device_t dev)
{
struct dwmmc_softc *sc;
sc = device_get_softc(dev);
- sc->hwtype = HWTYPE_HISILICON;
- /* TODO: Calculate this from a clock driver */
- sc->bus_hz = 24000000; /* 24MHz */
+ sc->hwtype = HWTYPE_ALTERA;
- /*
- * ARM64TODO: This is likely because we lack support for
- * DMA when the controller is not cache-coherent on arm64.
- */
- sc->use_pio = 1;
- sc->desc_count = 1;
-
return (dwmmc_attach(dev));
}
-static device_method_t hisi_dwmmc_methods[] = {
+static device_method_t altera_dwmmc_methods[] = {
/* bus interface */
- DEVMETHOD(device_probe, hisi_dwmmc_probe),
- DEVMETHOD(device_attach, hisi_dwmmc_attach),
+ DEVMETHOD(device_probe, altera_dwmmc_probe),
+ DEVMETHOD(device_attach, altera_dwmmc_attach),
DEVMETHOD_END
};
-static devclass_t hisi_dwmmc_devclass;
+static devclass_t altera_dwmmc_devclass;
-DEFINE_CLASS_1(hisi_dwmmc, hisi_dwmmc_driver, hisi_dwmmc_methods,
+DEFINE_CLASS_1(altera_dwmmc, altera_dwmmc_driver, altera_dwmmc_methods,
sizeof(struct dwmmc_softc), dwmmc_driver);
-DRIVER_MODULE(hisi_dwmmc, simplebus, hisi_dwmmc_driver,
- hisi_dwmmc_devclass, 0, 0);
+
+DRIVER_MODULE(altera_dwmmc, simplebus, altera_dwmmc_driver,
+ altera_dwmmc_devclass, 0, 0);
+DRIVER_MODULE(altera_dwmmc, ofwbus, altera_dwmmc_driver, altera_dwmmc_devclass
+ , NULL, NULL);
+#ifndef MMCCAM
+MMC_DECLARE_BRIDGE(altera_dwmmc);
+#endif
Modified: head/sys/dev/mmc/host/dwmmc_hisi.c
==============================================================================
--- head/sys/dev/mmc/host/dwmmc_hisi.c Sat Dec 30 20:28:29 2017 (r327391)
+++ head/sys/dev/mmc/host/dwmmc_hisi.c Sat Dec 30 22:01:17 2017 (r327392)
@@ -92,5 +92,11 @@ static devclass_t hisi_dwmmc_devclass;
DEFINE_CLASS_1(hisi_dwmmc, hisi_dwmmc_driver, hisi_dwmmc_methods,
sizeof(struct dwmmc_softc), dwmmc_driver);
+
DRIVER_MODULE(hisi_dwmmc, simplebus, hisi_dwmmc_driver,
hisi_dwmmc_devclass, 0, 0);
+DRIVER_MODULE(hisi_dwmmc, ofwbus, hisi_dwmmc_driver, hisi_dwmmc_devclass
+ , NULL, NULL);
+#ifndef MMCCAM
+MMC_DECLARE_BRIDGE(hisi_dwmmc);
+#endif
Copied and modified: head/sys/dev/mmc/host/dwmmc_rockchip.c (from r327391, head/sys/dev/mmc/host/dwmmc_hisi.c)
==============================================================================
--- head/sys/dev/mmc/host/dwmmc_hisi.c Sat Dec 30 20:28:29 2017 (r327391, copy source)
+++ head/sys/dev/mmc/host/dwmmc_rockchip.c Sat Dec 30 22:01:17 2017 (r327392)
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Andrew Turner.
+ * Copyright 2017 Emmanuel Vadot <manu at freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -41,56 +41,58 @@ __FBSDID("$FreeBSD$");
#include <dev/mmc/host/dwmmc_var.h>
-static device_probe_t hisi_dwmmc_probe;
-static device_attach_t hisi_dwmmc_attach;
+static struct ofw_compat_data compat_data[] = {
+ {"rockchip,rk2928-dw-mshc", 1},
+ {NULL, 0},
+};
static int
-hisi_dwmmc_probe(device_t dev)
+rockchip_dwmmc_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (!ofw_bus_is_compatible(dev, "hisilicon,hi6220-dw-mshc"))
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "Synopsys DesignWare Mobile "
- "Storage Host Controller (HiSilicon)");
+ "Storage Host Controller (RockChip)");
return (BUS_PROBE_VENDOR);
}
static int
-hisi_dwmmc_attach(device_t dev)
+rockchip_dwmmc_attach(device_t dev)
{
struct dwmmc_softc *sc;
sc = device_get_softc(dev);
- sc->hwtype = HWTYPE_HISILICON;
- /* TODO: Calculate this from a clock driver */
- sc->bus_hz = 24000000; /* 24MHz */
+ sc->hwtype = HWTYPE_ROCKCHIP;
- /*
- * ARM64TODO: This is likely because we lack support for
- * DMA when the controller is not cache-coherent on arm64.
- */
sc->use_pio = 1;
- sc->desc_count = 1;
+ sc->pwren_inverted = 1;
return (dwmmc_attach(dev));
}
-static device_method_t hisi_dwmmc_methods[] = {
+static device_method_t rockchip_dwmmc_methods[] = {
/* bus interface */
- DEVMETHOD(device_probe, hisi_dwmmc_probe),
- DEVMETHOD(device_attach, hisi_dwmmc_attach),
+ DEVMETHOD(device_probe, rockchip_dwmmc_probe),
+ DEVMETHOD(device_attach, rockchip_dwmmc_attach),
DEVMETHOD_END
};
-static devclass_t hisi_dwmmc_devclass;
+static devclass_t rockchip_dwmmc_devclass;
-DEFINE_CLASS_1(hisi_dwmmc, hisi_dwmmc_driver, hisi_dwmmc_methods,
+DEFINE_CLASS_1(rockchip_dwmmc, rockchip_dwmmc_driver, rockchip_dwmmc_methods,
sizeof(struct dwmmc_softc), dwmmc_driver);
-DRIVER_MODULE(hisi_dwmmc, simplebus, hisi_dwmmc_driver,
- hisi_dwmmc_devclass, 0, 0);
+
+DRIVER_MODULE(rockchip_dwmmc, simplebus, rockchip_dwmmc_driver,
+ rockchip_dwmmc_devclass, 0, 0);
+DRIVER_MODULE(rockchip_dwmmc, ofwbus, rockchip_dwmmc_driver,
+ rockchip_dwmmc_devclass, NULL, NULL);
+#ifndef MMCCAM
+MMC_DECLARE_BRIDGE(rockchip_dwmmc);
+#endif
Added: head/sys/dev/mmc/host/dwmmc_samsung.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/mmc/host/dwmmc_samsung.c Sat Dec 30 22:01:17 2017 (r327392)
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2017 Emmanuel Vadot <manu at freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+
+#include <dev/mmc/bridge.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/mmc/host/dwmmc_var.h>
+#include <dev/mmc/host/dwmmc_reg.h>
+
+#define WRITE4(_sc, _reg, _val) \
+ bus_write_4((_sc)->res[0], _reg, _val)
+
+static struct ofw_compat_data compat_data[] = {
+ {"samsung,exynos5420-dw-mshc", 1},
+ {NULL, 0},
+};
+
+static int
+samsung_dwmmc_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+ return (ENXIO);
+
+ device_set_desc(dev, "Synopsys DesignWare Mobile "
+ "Storage Host Controller (Samsung)");
+
+ return (BUS_PROBE_VENDOR);
+}
+
+static int
+samsung_dwmmc_attach(device_t dev)
+{
+ struct dwmmc_softc *sc;
+ pcell_t dts_value[3];
+ phandle_t node;
+ int len;
+
+ sc = device_get_softc(dev);
+ sc->hwtype = HWTYPE_EXYNOS;
+
+ if ((node = ofw_bus_get_node(sc->dev)) == -1)
+ return (ENXIO);
+
+ if ((len = OF_getproplen(node, "samsung,dw-mshc-ciu-div")) <= 0)
+ return (ENXIO);
+ OF_getencprop(node, "samsung,dw-mshc-ciu-div", dts_value, len);
+ sc->sdr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT);
+ sc->ddr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT);
+
+ if ((len = OF_getproplen(node, "samsung,dw-mshc-sdr-timing")) <= 0)
+ return (ENXIO);
+ OF_getencprop(node, "samsung,dw-mshc-sdr-timing", dts_value, len);
+ sc->sdr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) |
+ (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT));
+
+ if ((len = OF_getproplen(node, "samsung,dw-mshc-ddr-timing")) <= 0)
+ return (ENXIO);
+ OF_getencprop(node, "samsung,dw-mshc-ddr-timing", dts_value, len);
+ sc->ddr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) |
+ (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT));
+
+ WRITE4(sc, EMMCP_MPSBEGIN0, 0);
+ WRITE4(sc, EMMCP_SEND0, 0);
+ WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |
+ MPSCTRL_SECURE_WRITE_BIT |
+ MPSCTRL_NON_SECURE_READ_BIT |
+ MPSCTRL_NON_SECURE_WRITE_BIT |
+ MPSCTRL_VALID));
+
+ return (dwmmc_attach(dev));
+}
+
+static device_method_t samsung_dwmmc_methods[] = {
+ /* bus interface */
+ DEVMETHOD(device_probe, samsung_dwmmc_probe),
+ DEVMETHOD(device_attach, samsung_dwmmc_attach),
+
+ DEVMETHOD_END
+};
+
+static devclass_t samsung_dwmmc_devclass;
+
+DEFINE_CLASS_1(samsung_dwmmc, samsung_dwmmc_driver, samsung_dwmmc_methods,
+ sizeof(struct dwmmc_softc), dwmmc_driver);
+
+DRIVER_MODULE(samsung_dwmmc, simplebus, samsung_dwmmc_driver,
+ samsung_dwmmc_devclass, 0, 0);
+DRIVER_MODULE(samsung_dwmmc, ofwbus, samsung_dwmmc_driver, samsung_dwmmc_devclass
+ , NULL, NULL);
+#ifndef MMCCAM
+MMC_DECLARE_BRIDGE(samsung_dwmmc);
+#endif
Modified: head/sys/dev/mmc/host/dwmmc_var.h
==============================================================================
--- head/sys/dev/mmc/host/dwmmc_var.h Sat Dec 30 20:28:29 2017 (r327391)
+++ head/sys/dev/mmc/host/dwmmc_var.h Sat Dec 30 22:01:17 2017 (r327392)
@@ -74,7 +74,7 @@ struct dwmmc_softc {
uint32_t ddr_timing;
};
-extern driver_t dwmmc_driver;
+DECLARE_CLASS(dwmmc_driver);
int dwmmc_attach(device_t);
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