svn commit: r326977 - head/sys/dev/mlx5/mlx5_en

Konstantin Belousov kib at FreeBSD.org
Tue Dec 19 14:11:42 UTC 2017


Author: kib
Date: Tue Dec 19 14:11:41 2017
New Revision: 326977
URL: https://svnweb.freebsd.org/changeset/base/326977

Log:
  mlx5en: Avoid SFENCe on x86
  
  The IA32 memory model guarantees that all writes are seen in the program
  order.  Also, any access to the uncacheable memory flushes the store
  buffers.  As the consequence, SFENCE instruction is (almost) never needed,
  in particular, it is not needed to ensure the correct order of updates as
  seen by a PCIe device.
  
  Use atomic_thread_fence_rel() instead of wb() to only emit compiler barriers
  on x86 there.  Other architectures get the right barrier instruction as
  well.
  
  Reviewed by:	hselasky
  Sponsored by:	Mellanox Technologies
  MFC after:	1 week

Modified:
  head/sys/dev/mlx5/mlx5_en/mlx5_en_rx.c

Modified: head/sys/dev/mlx5/mlx5_en/mlx5_en_rx.c
==============================================================================
--- head/sys/dev/mlx5/mlx5_en/mlx5_en_rx.c	Tue Dec 19 11:44:24 2017	(r326976)
+++ head/sys/dev/mlx5/mlx5_en/mlx5_en_rx.c	Tue Dec 19 14:11:41 2017	(r326977)
@@ -90,7 +90,7 @@ mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 	}
 
 	/* ensure wqes are visible to device before updating doorbell record */
-	wmb();
+	atomic_thread_fence_rel();
 
 	mlx5_wq_ll_update_db_record(&rq->wq);
 }
@@ -436,7 +436,7 @@ wq_ll_pop:
 	mlx5_cqwq_update_db_record(&rq->cq.wq);
 
 	/* ensure cq space is freed before enabling more cqes */
-	wmb();
+	atomic_thread_fence_rel();
 	return (i);
 }
 


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