svn commit: r323032 - in head: share/man/man4 sys/amd64/conf sys/conf sys/dev/ntb/ntb_hw sys/i386/conf sys/modules/ntb sys/modules/ntb/ntb_hw sys/modules/ntb/ntb_hw_intel sys/modules/ntb/ntb_hw_plx
Alexander Motin
mav at FreeBSD.org
Wed Aug 30 21:16:35 UTC 2017
Author: mav
Date: Wed Aug 30 21:16:32 2017
New Revision: 323032
URL: https://svnweb.freebsd.org/changeset/base/323032
Log:
Add NTB driver for PLX/Avago/Broadcom PCIe switches.
This driver supports both NTB-to-NTB and NTB-to-Root Port modes (though
the second with predictable complications on hot-plug and reboot events).
I tested it with PEX 8717 and PEX 8733 chips, but expect it should work
with many other compatible ones too. It supports up to two NT bridges
per chip, each of which can have up to 2 64-bit or 4 32-bit memory windows,
6 or 12 scratchpad registers and 16 doorbells. There are also 4 DMA engines
in those chips, but they are not yet supported.
While there, rename Intel NTB driver from generic ntb_hw(4) to more specific
ntb_hw_intel(4), so now it is on par with this new ntb_hw_plx(4) driver and
alike to Linux naming.
MFC after: 2 weeks
Sponsored by: iXsystems, Inc.
Added:
head/share/man/man4/ntb.4 (contents, props changed)
head/share/man/man4/ntb_hw_intel.4
- copied, changed from r323031, head/share/man/man4/ntb_hw.4
head/share/man/man4/ntb_hw_plx.4 (contents, props changed)
head/sys/dev/ntb/ntb_hw/ntb_hw_intel.c
- copied, changed from r323031, head/sys/dev/ntb/ntb_hw/ntb_hw.c
head/sys/dev/ntb/ntb_hw/ntb_hw_intel.h
- copied unchanged from r323031, head/sys/dev/ntb/ntb_hw/ntb_regs.h
head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c (contents, props changed)
head/sys/modules/ntb/ntb_hw_intel/
- copied from r323031, head/sys/modules/ntb/ntb_hw/
head/sys/modules/ntb/ntb_hw_plx/
head/sys/modules/ntb/ntb_hw_plx/Makefile (contents, props changed)
Deleted:
head/share/man/man4/ntb_hw.4
head/sys/dev/ntb/ntb_hw/ntb_hw.c
head/sys/dev/ntb/ntb_hw/ntb_regs.h
head/sys/modules/ntb/ntb_hw/
Modified:
head/share/man/man4/Makefile
head/share/man/man4/if_ntb.4
head/share/man/man4/ntb_transport.4
head/sys/amd64/conf/NOTES
head/sys/conf/files.amd64
head/sys/conf/files.i386
head/sys/i386/conf/NOTES
head/sys/modules/ntb/Makefile
head/sys/modules/ntb/ntb_hw_intel/Makefile
Modified: head/share/man/man4/Makefile
==============================================================================
--- head/share/man/man4/Makefile Wed Aug 30 20:00:15 2017 (r323031)
+++ head/share/man/man4/Makefile Wed Aug 30 21:16:32 2017 (r323032)
@@ -373,7 +373,9 @@ MAN= aac.4 \
ng_vlan.4 \
nmdm.4 \
nsp.4 \
- ${_ntb_hw.4} \
+ ${_ntb.4} \
+ ${_ntb_hw_intel.4} \
+ ${_ntb_hw_plx.4} \
${_ntb_transport.4} \
${_if_ntb.4} \
null.4 \
@@ -686,7 +688,6 @@ MLINKS+=netintro.4 net.4 \
netintro.4 networking.4
MLINKS+=${_nfe.4} ${_if_nfe.4}
MLINKS+=nge.4 if_nge.4
-MLINKS+=${_ntb_hw.4} ${_ntb.4}
MLINKS+=${_nxge.4} ${_if_nxge.4}
MLINKS+=ow.4 onewire.4
MLINKS+=pccbb.4 cbb.4
@@ -834,7 +835,8 @@ _xnb.4= xnb.4
_if_ntb.4= if_ntb.4
_ioat.4= ioat.4
_ntb.4= ntb.4
-_ntb_hw.4= ntb_hw.4
+_ntb_hw_intel.4= ntb_hw_intel.4
+_ntb_hw_plx.4= ntb_hw_plx.4
_ntb_transport.4=ntb_transport.4
_qlxge.4= qlxge.4
_qlxgb.4= qlxgb.4
Modified: head/share/man/man4/if_ntb.4
==============================================================================
--- head/share/man/man4/if_ntb.4 Wed Aug 30 20:00:15 2017 (r323031)
+++ head/share/man/man4/if_ntb.4 Wed Aug 30 21:16:32 2017 (r323032)
@@ -25,7 +25,7 @@
.\"
.\" $FreeBSD$
.\"
-.Dd July 29, 2016
+.Dd August 30, 2017
.Dt IF_NTB 4
.Os
.Sh NAME
@@ -35,6 +35,8 @@
To compile this driver into your kernel,
place the following lines in your kernel configuration file:
.Bd -ragged -offset indent
+.Cd "device ntb"
+.Cd "device ntb_transport"
.Cd "device if_ntb"
.Ed
.Pp
@@ -56,11 +58,11 @@ The
.Nm
driver attaches on top of the
.Xr ntb_transport 4
-driver to utilize its resources to create virtual Ethernet interface between
-the systems.
-Interface capabilities depend on the underlying transport.
+driver to utilize its resources to create virtual Ethernet network interface
+between the systems.
+It supports as many tx/rx queues as provided by underlying
+.Xr ntb_transport 4 .
Typical MTU is about 64KB to reduce overhead.
-By default one queue is used, but more may be configured.
The MAC address for interface is randomly generated.
.Pp
The
Added: head/share/man/man4/ntb.4
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/share/man/man4/ntb.4 Wed Aug 30 21:16:32 2017 (r323032)
@@ -0,0 +1,91 @@
+.\"
+.\" Copyright (c) 2017 Alexander Motin <mav at FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd August 30, 2017
+.Dt NTB 4
+.Os
+.Sh NAME
+.Nm ntb
+.Nd Non-Transparent Bridge subsystem
+.Sh SYNOPSIS
+To compile it into your kernel,
+place the following lines in your kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device ntb"
+.Ed
+.Pp
+Or, to load it as a module at boot, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+ntb_load="YES"
+.Ed
+.Pp
+The following tunables are settable from the
+.Xr loader 8 :
+.Bl -ohang
+.It Va hw.ntb.debug_level
+Driver debug level.
+The default value is 0, higher means more verbose.
+.It Va hint.ntb_hw. Ns Ar X Ns Va .config
+Configures NTB resources split between several consumer devices.
+Configuration of multiple consumer devices separated by commas.
+Each device can be configured as: "[<name>][:<mw>[:<spad>[:<db>]]]", where:
+.Va name
+is a name of the driver which should attach the device (empty means any),
+.Va mw
+is a number of memory windows to allocate (empty means all available),
+.Va spad
+is a number of scratchpad registers to allocate (empty means all available),
+.Va db
+is a number of doorbells to allocate (empty means all available).
+The default configuration is empty string, which means single device
+with all available resources allowing any driver attachment.
+.El
+.Sh DESCRIPTION
+Non-Transparent Bridges allow to connect two computer systems with PCIe
+link(s), providing each of them limited access to others memory space,
+scratchpad registers and interrupts.
+The
+.Nm
+subsystem uses those resources provided in generic way by hardware drivers
+and splits them between multiple consumer drivers, according to specified
+configuration.
+.Sh SEE ALSO
+.Xr if_ntb 4 ,
+.Xr ntb_transport 4 ,
+.Xr ntb_hw_intel 4 ,
+.Xr ntb_hw_plx 4
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+subsystem was developed by Intel and originally written by
+.An Carl Delsey Aq Mt carl at FreeBSD.org .
+Later improvements were done by
+.An Conrad E. Meyer Aq Mt cem at FreeBSD.org
+and
+.An Alexander Motin Aq Mt mav at FreeBSD.org .
Copied and modified: head/share/man/man4/ntb_hw_intel.4 (from r323031, head/share/man/man4/ntb_hw.4)
==============================================================================
--- head/share/man/man4/ntb_hw.4 Wed Aug 30 20:00:15 2017 (r323031, copy source)
+++ head/share/man/man4/ntb_hw_intel.4 Wed Aug 30 21:16:32 2017 (r323032)
@@ -1,5 +1,5 @@
.\"
-.\" Copyright (c) 2016 Alexander Motin <mav at FreeBSD.org>
+.\" Copyright (c) 2016-2017 Alexander Motin <mav at FreeBSD.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -25,66 +25,45 @@
.\"
.\" $FreeBSD$
.\"
-.Dd July 28, 2016
-.Dt NTB_HW 4
+.Dd August 30, 2017
+.Dt NTB_HW_INTEL 4
.Os
.Sh NAME
-.Nm ntb ,
-.Nm ntb_hw
+.Nm ntb_hw_intel
.Nd Intel(R) Non-Transparent Bridge driver
.Sh SYNOPSIS
To compile this driver into your kernel,
place the following lines in your kernel configuration file:
.Bd -ragged -offset indent
-.Cd "device ntb_hw"
+.Cd "device ntb"
+.Cd "device ntb_hw_intel"
.Ed
.Pp
Or, to load the driver as a module at boot, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
-ntb_hw_load="YES"
+ntb_hw_intel_load="YES"
.Ed
-.Pp
-The following tunables are settable from the
-.Xr loader 8 :
-.Bl -ohang
-.It Va hw.ntb.debug_level
-Driver debug level.
-The default value is 0, higher means more verbose.
-.It Va hint.ntb_hw. Ns Ar X Ns Va .config
-Configures NTB resources split between several consumer devices.
-Configuration of multiple consumer devices separated by commas.
-Each device can be configured as: "<name>[:<mw>[:<spad>[:<db>]]]", where:
-.Va name
-is a name of the driver which should attach the device (empty means any),
-.Va mw
-is a number of memory windows to allocate (empty means all available),
-.Va spad
-is a number of scratchpad registers to allocate (empty means all available),
-.Va db
-is a number of doorbells to allocate (empty means all available).
-The default configuration is empty string, which means single device
-with all available resources allowing any driver attachment.
-.El
.Sh DESCRIPTION
-The NTB allows you to connect two computer systems using a PCIe link if they
-have the correct equipment and connectors.
The
-.Nm ntb_hw
-driver provides support for the Non-Transparent Bridge (NTB) in the Intel S1200
-and Xeon E3/E5 processor families.
-The
-.Nm
-driver hides hardware details, exposing memory windows, scratchpads and
-doorbells via hardware independent KPI.
+.Nm ntb_hw_intel
+driver provides support for the Non-Transparent Bridge (NTB) hardware in
+Intel Xeon E3/E5 and S1200 processor families, which allow one of their PCIe
+ports to be switched from transparent to non-transparent bridge mode.
+In this mode bridge looks not as a PCI bridge, but as PCI endpoint device.
+The driver hides hardware details, exposing memory windows, scratchpads
+and doorbells of the other side via hardware independent KPI to
+.Xr ntb 4
+subsystem.
.Pp
-The hardware provides 2-3 memory windows to the other system's memory,
-16 scratchpad registers and 14/34 doorbells to interrupt the other system.
+The hardware provides 2 or 3 memory windows to the other system's memory,
+16 scratchpad registers and 14 or 34 doorbells to interrupt the other system.
On Xeon processors one of memory windows is typically consumed by the driver
-to workaround multiple hardware erratas.
+itself to workaround multiple hardware erratas.
.Sh CONFIGURATION
The NTB configuration should be set by BIOS.
-It includes enabling NTB, choosing between NTB-to-NTB or NTB-to-Root Port mode,
+It includes enabling NTB, choosing between NTB-to-NTB (back-to-back) or
+NTB-to-Root Port mode,
enabling split BAR mode (one of two 64-bit BARs can be split into two 32-bit
ones) and configuring BAR sizes in bits (from 12 to 29/39) for both NTB sides.
.Pp
@@ -93,7 +72,8 @@ all BAR sizes are set to 20 (1 MiB).
This needs to be done on both systems.
.Sh SEE ALSO
.Xr if_ntb 4 ,
-.Xr ntb_transport 4
+.Xr ntb_transport 4 ,
+.Xr ntb 4 ,
.Sh AUTHORS
.An -nosplit
The
Added: head/share/man/man4/ntb_hw_plx.4
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/share/man/man4/ntb_hw_plx.4 Wed Aug 30 21:16:32 2017 (r323032)
@@ -0,0 +1,118 @@
+.\"
+.\" Copyright (c) 2017 Alexander Motin <mav at FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd August 30, 2017
+.Dt NTB_HW_PLX 4
+.Os
+.Sh NAME
+.Nm ntb_hw_plx
+.Nd PLX/Avago/Broadcom Non-Transparent Bridge driver
+.Sh SYNOPSIS
+To compile this driver into your kernel,
+place the following lines in your kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device ntb"
+.Cd "device ntb_hw_plx"
+.Ed
+.Pp
+Or, to load the driver as a module at boot, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+ntb_hw_plx_load="YES"
+.Ed
+.Pp
+The following tunables are settable from the
+.Xr loader 8 :
+.Bl -ohang
+.It Va hint.ntb_hw. Ns Ar X Ns Va .b2b
+Being set to 1 (default) tells the driver attached to Virtual Interface of the
+NTB that it works in NTB-to-NTB (back-to-back) mode, 0 -- NTB-to-Root Port.
+Driver attached to Link Interface (visible from Root Port side) switches to
+NTB-to-Root Port mode automatically, but one attached to Virtual Interface
+can't detect what is on the other side and require external knowledge.
+.El
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the Non-Transparent Bridge (NTB) hardware in
+PLX PCIe bridge chips, which allow up to two of their PCIe ports to be
+switched from transparent to non-transparent bridge mode.
+In this mode bridge looks not as a PCI bridge, but as PCI endpoint device.
+The driver hides hardware details, exposing memory windows, scratchpads
+and doorbells of the other side via hardware independent KPI to
+.Xr ntb 4
+subsystem.
+.Pp
+Each PLX NTB provides up to 2 64-bit or 4 32-bit memory windows to the
+other system's memory, 6 or 12 scratchpad registers and 16 doorbells to
+interrupt the other system.
+In NTB-to-NTB mode one of memory windows (or half of it, if bigger then 1MB)
+is consumed by the driver itself to access scratchpad and doorbell registers
+of the other side.
+.Sh HARDWARE
+The following PLX/Avago/Broadcom chips are supported by the
+.Nm
+driver:
+.Pp
+.Bl -bullet -compact
+.It
+PEX 8713
+.It
+PEX 8717
+.It
+PEX 8725
+.It
+PEX 8733
+.It
+PEX 8749
+.El
+.Pp
+, but it may also work with other compatible ones.
+.Sh CONFIGURATION
+The basic chip configuration should be done by serial EEPROM or via i2c.
+It includes enabling NTB on one or both sides (choosing between NTB-to-NTB
+(back-to-back) and NTB-to-Root Port modes) and configuring BARs sizes.
+.Pp
+The recommended mode is NTB-to-NTB mode, since while NTB-to-Root Port is
+generally supported by the driver, it require PCI hotplug handling on the
+Root Port, that may be difficult or cause different kinds of problems.
+.Sh SEE ALSO
+.Xr if_ntb 4 ,
+.Xr ntb_transport 4 ,
+.Xr ntb 4 ,
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An Alexander Motin Aq Mt mav at FreeBSD.org .
+.Sh BUGS
+There is no way to protect your system from malicious behavior on the other
+system once the link is brought up.
+Anyone with root or kernel access on the other system can read or write to
+any location on your system.
+In other words, only connect two systems that completely trust each other.
Modified: head/share/man/man4/ntb_transport.4
==============================================================================
--- head/share/man/man4/ntb_transport.4 Wed Aug 30 20:00:15 2017 (r323031)
+++ head/share/man/man4/ntb_transport.4 Wed Aug 30 21:16:32 2017 (r323032)
@@ -1,5 +1,5 @@
.\"
-.\" Copyright (c) 2016 Alexander Motin <mav at FreeBSD.org>
+.\" Copyright (c) 2016-2017 Alexander Motin <mav at FreeBSD.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
@@ -25,14 +25,21 @@
.\"
.\" $FreeBSD$
.\"
-.Dd July 29, 2016
+.Dd August 30, 2017
.Dt NTB_TRANSPORT 4
.Os
.Sh NAME
.Nm ntb_transport
.Nd Packet-oriented transport for Non-Transparent Bridges
.Sh SYNOPSIS
-To load the driver as a module at boot, place the following line in
+To compile this driver into your kernel,
+place the following lines in your kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device ntb"
+.Cd "device ntb_transport"
+.Ed
+.Pp
+Or, to load the driver as a module at boot, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
ntb_transport_load="YES"
@@ -46,11 +53,11 @@ Driver debug level.
The default value is 0, higher means more verbose.
.It Va hint.ntb_transport. Ns Ar X Ns Va .config
Configures queues allocation for consumer devices, separated by commas.
-Each device can be configured as: "<name>[:<queues>]", where:
+Each device can be configured as: "[<name>][:<queues>]", where:
.Va name
is a name of the driver which should attach the device (empty means any),
.Va queues
-is a number of queues to allocate (empty means automatic),
+is a number of queues to allocate (empty means automatic).
The default configuration is empty string, which means single device
with one queue per memory window allowing any driver attachment.
.El
@@ -64,9 +71,25 @@ delivering packets between the systems.
The primary purpose of this is to be used by
.Nm if_ntb
network interface, but other consumers may also be developed using KPI.
+.Pp
+Each
+.Nm
+require from underlying
+.Nm ntb
+instance:
+.Bl -bullet -compact
+.It
+1 or more memory windows;
+.It
+6 scratchpads, plus 2 more for each additional memory window;
+.It
+1 doorbell for each memory window or configured queue.
+.El
.Sh SEE ALSO
.Xr if_ntb 4 ,
-.Xr ntb_hw 4
+.Xr ntb 4 ,
+.Xr ntb_hw_intel 4 ,
+.Xr ntb_hw_plx 4
.Sh AUTHORS
.An -nosplit
The
Modified: head/sys/amd64/conf/NOTES
==============================================================================
--- head/sys/amd64/conf/NOTES Wed Aug 30 20:00:15 2017 (r323031)
+++ head/sys/amd64/conf/NOTES Wed Aug 30 21:16:32 2017 (r323032)
@@ -395,9 +395,14 @@ device iwn6000g2bfw
device iwn6050fw
device wpifw
-# Intel Non-Transparent Bridge (NTB) hardware
-device ntb_hw # Hardware Abstraction Layer for the NTB
-device if_ntb # Simulated ethernet device using the NTB
+#
+# Non-Transparent Bridge (NTB) drivers
+#
+device if_ntb # Virtual NTB network interface
+device ntb_transport # NTB packet transport driver
+device ntb # NTB hardware interface
+device ntb_hw_intel # Intel NTB hardware driver
+device ntb_hw_plx # PLX NTB hardware driver
#
#XXX this stores pointers in a 32bit field that is defined by the hardware
Modified: head/sys/conf/files.amd64
==============================================================================
--- head/sys/conf/files.amd64 Wed Aug 30 20:00:15 2017 (r323031)
+++ head/sys/conf/files.amd64 Wed Aug 30 21:16:32 2017 (r323032)
@@ -330,10 +330,11 @@ dev/hyperv/vmbus/amd64/vmbus_vector.S optional hyper
dev/nctgpio/nctgpio.c optional nctgpio
dev/nfe/if_nfe.c optional nfe pci
dev/ntb/if_ntb/if_ntb.c optional if_ntb
-dev/ntb/ntb_transport.c optional if_ntb
-dev/ntb/ntb.c optional if_ntb | ntb_hw
-dev/ntb/ntb_if.m optional if_ntb | ntb_hw
-dev/ntb/ntb_hw/ntb_hw.c optional ntb_hw
+dev/ntb/ntb_transport.c optional ntb_transport | if_ntb
+dev/ntb/ntb.c optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx | ntb_hw
+dev/ntb/ntb_if.m optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx | ntb_hw
+dev/ntb/ntb_hw/ntb_hw_intel.c optional ntb_hw_intel | ntb_hw
+dev/ntb/ntb_hw/ntb_hw_plx.c optional ntb_hw_plx | ntb_hw
dev/nvd/nvd.c optional nvd nvme
dev/nvme/nvme.c optional nvme
dev/nvme/nvme_ctrlr.c optional nvme
Modified: head/sys/conf/files.i386
==============================================================================
--- head/sys/conf/files.i386 Wed Aug 30 20:00:15 2017 (r323031)
+++ head/sys/conf/files.i386 Wed Aug 30 21:16:32 2017 (r323032)
@@ -271,10 +271,11 @@ dev/mse/mse_isa.c optional mse isa
dev/nctgpio/nctgpio.c optional nctgpio
dev/nfe/if_nfe.c optional nfe pci
dev/ntb/if_ntb/if_ntb.c optional if_ntb
-dev/ntb/ntb_transport.c optional if_ntb
-dev/ntb/ntb.c optional if_ntb | ntb_hw
-dev/ntb/ntb_if.m optional if_ntb | ntb_hw
-dev/ntb/ntb_hw/ntb_hw.c optional ntb_hw
+dev/ntb/ntb_transport.c optional ntb_transport | if_ntb
+dev/ntb/ntb.c optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx
+dev/ntb/ntb_if.m optional ntb | ntb_transport | if_ntb | ntb_hw_intel | ntb_hw_plx
+dev/ntb/ntb_hw/ntb_hw_intel.c optional ntb_hw_intel
+dev/ntb/ntb_hw/ntb_hw_plx.c optional ntb_hw_plx
dev/nvd/nvd.c optional nvd nvme
dev/nvme/nvme.c optional nvme
dev/nvme/nvme_ctrlr.c optional nvme
Copied and modified: head/sys/dev/ntb/ntb_hw/ntb_hw_intel.c (from r323031, head/sys/dev/ntb/ntb_hw/ntb_hw.c)
==============================================================================
--- head/sys/dev/ntb/ntb_hw/ntb_hw.c Wed Aug 30 20:00:15 2017 (r323031, copy source)
+++ head/sys/dev/ntb/ntb_hw/ntb_hw_intel.c Wed Aug 30 21:16:32 2017 (r323032)
@@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
-#include "ntb_regs.h"
+#include "ntb_hw_intel.h"
#include "../ntb.h"
#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT)
@@ -3116,6 +3116,6 @@ static device_method_t ntb_intel_methods[] = {
static DEFINE_CLASS_0(ntb_hw, ntb_intel_driver, ntb_intel_methods,
sizeof(struct ntb_softc));
-DRIVER_MODULE(ntb_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL);
-MODULE_DEPEND(ntb_intel, ntb, 1, 1, 1);
-MODULE_VERSION(ntb_intel, 1);
+DRIVER_MODULE(ntb_hw_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL);
+MODULE_DEPEND(ntb_hw_intel, ntb, 1, 1, 1);
+MODULE_VERSION(ntb_hw_intel, 1);
Copied: head/sys/dev/ntb/ntb_hw/ntb_hw_intel.h (from r323031, head/sys/dev/ntb/ntb_hw/ntb_regs.h)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/ntb/ntb_hw/ntb_hw_intel.h Wed Aug 30 21:16:32 2017 (r323032, copy of r323031, head/sys/dev/ntb/ntb_hw/ntb_regs.h)
@@ -0,0 +1,168 @@
+/*-
+ * Copyright (c) 2016 Alexander Motin <mav at FreeBSD.org>
+ * Copyright (C) 2013 Intel Corporation
+ * Copyright (C) 2015 EMC Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _NTB_REGS_H_
+#define _NTB_REGS_H_
+
+#define NTB_LINK_STATUS_ACTIVE 0x2000
+#define NTB_LINK_SPEED_MASK 0x000f
+#define NTB_LINK_WIDTH_MASK 0x03f0
+#define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4)
+
+#define XEON_SNB_MW_COUNT 2
+#define XEON_HSX_SPLIT_MW_COUNT 3
+/* Reserve the uppermost bit for link interrupt */
+#define XEON_DB_COUNT 15
+#define XEON_DB_TOTAL_SHIFT 16
+#define XEON_DB_LINK 15
+#define XEON_DB_MSIX_VECTOR_COUNT 4
+#define XEON_DB_MSIX_VECTOR_SHIFT 5
+#define XEON_DB_LINK_BIT (1 << XEON_DB_LINK)
+#define XEON_NONLINK_DB_MSIX_BITS 3
+
+#define XEON_SPCICMD_OFFSET 0x0504
+#define XEON_DEVCTRL_OFFSET 0x0598
+#define XEON_DEVSTS_OFFSET 0x059a
+#define XEON_LINK_STATUS_OFFSET 0x01a2
+#define XEON_SLINK_STATUS_OFFSET 0x05a2
+
+#define XEON_PBAR2LMT_OFFSET 0x0000
+#define XEON_PBAR4LMT_OFFSET 0x0008
+#define XEON_PBAR5LMT_OFFSET 0x000c
+#define XEON_PBAR2XLAT_OFFSET 0x0010
+#define XEON_PBAR4XLAT_OFFSET 0x0018
+#define XEON_PBAR5XLAT_OFFSET 0x001c
+#define XEON_SBAR2LMT_OFFSET 0x0020
+#define XEON_SBAR4LMT_OFFSET 0x0028
+#define XEON_SBAR5LMT_OFFSET 0x002c
+#define XEON_SBAR2XLAT_OFFSET 0x0030
+#define XEON_SBAR4XLAT_OFFSET 0x0038
+#define XEON_SBAR5XLAT_OFFSET 0x003c
+#define XEON_SBAR0BASE_OFFSET 0x0040
+#define XEON_SBAR2BASE_OFFSET 0x0048
+#define XEON_SBAR4BASE_OFFSET 0x0050
+#define XEON_SBAR5BASE_OFFSET 0x0054
+#define XEON_NTBCNTL_OFFSET 0x0058
+#define XEON_SBDF_OFFSET 0x005c
+#define XEON_PDOORBELL_OFFSET 0x0060
+#define XEON_PDBMSK_OFFSET 0x0062
+#define XEON_SDOORBELL_OFFSET 0x0064
+#define XEON_SDBMSK_OFFSET 0x0066
+#define XEON_USMEMMISS_OFFSET 0x0070
+#define XEON_SPAD_OFFSET 0x0080
+#define XEON_SPAD_COUNT 16
+#define XEON_SPADSEMA4_OFFSET 0x00c0
+#define XEON_WCCNTRL_OFFSET 0x00e0
+#define XEON_UNCERRSTS_OFFSET 0x014c
+#define XEON_CORERRSTS_OFFSET 0x0158
+#define XEON_B2B_SPAD_OFFSET 0x0100
+#define XEON_B2B_DOORBELL_OFFSET 0x0140
+#define XEON_B2B_XLAT_OFFSETL 0x0144
+#define XEON_B2B_XLAT_OFFSETU 0x0148
+
+#define ATOM_MW_COUNT 2
+#define ATOM_DB_COUNT 34
+#define ATOM_DB_MSIX_VECTOR_COUNT 34
+#define ATOM_DB_MSIX_VECTOR_SHIFT 1
+
+#define ATOM_SPCICMD_OFFSET 0xb004
+#define ATOM_MBAR23_OFFSET 0xb018
+#define ATOM_MBAR45_OFFSET 0xb020
+#define ATOM_DEVCTRL_OFFSET 0xb048
+#define ATOM_LINK_STATUS_OFFSET 0xb052
+#define ATOM_ERRCORSTS_OFFSET 0xb110
+
+#define ATOM_SBAR2XLAT_OFFSET 0x0008
+#define ATOM_SBAR4XLAT_OFFSET 0x0010
+#define ATOM_PDOORBELL_OFFSET 0x0020
+#define ATOM_PDBMSK_OFFSET 0x0028
+#define ATOM_NTBCNTL_OFFSET 0x0060
+#define ATOM_EBDF_OFFSET 0x0064
+#define ATOM_SPAD_OFFSET 0x0080
+#define ATOM_SPAD_COUNT 16
+#define ATOM_SPADSEMA_OFFSET 0x00c0
+#define ATOM_STKYSPAD_OFFSET 0x00c4
+#define ATOM_PBAR2XLAT_OFFSET 0x8008
+#define ATOM_PBAR4XLAT_OFFSET 0x8010
+#define ATOM_B2B_DOORBELL_OFFSET 0x8020
+#define ATOM_B2B_SPAD_OFFSET 0x8080
+#define ATOM_B2B_SPADSEMA_OFFSET 0x80c0
+#define ATOM_B2B_STKYSPAD_OFFSET 0x80c4
+
+#define ATOM_MODPHY_PCSREG4 0x1c004
+#define ATOM_MODPHY_PCSREG6 0x1c006
+
+#define ATOM_IP_BASE 0xc000
+#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
+#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
+#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
+#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
+
+#define ATOM_DESKEWSTS_DBERR (1 << 15)
+#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
+#define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
+#define ATOM_IBIST_ERR_OFLOW 0x7fff7fff
+
+#define NTB_CNTL_CFG_LOCK (1 << 0)
+#define NTB_CNTL_LINK_DISABLE (1 << 1)
+#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
+#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
+#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
+#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
+#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
+#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
+#define ATOM_CNTL_LINK_DOWN (1 << 16)
+
+#define XEON_PBAR23SZ_OFFSET 0x00d0
+#define XEON_PBAR45SZ_OFFSET 0x00d1
+#define XEON_PBAR4SZ_OFFSET 0x00d1
+#define XEON_PBAR5SZ_OFFSET 0x00d5
+#define XEON_SBAR23SZ_OFFSET 0x00d2
+#define XEON_SBAR4SZ_OFFSET 0x00d3
+#define XEON_SBAR5SZ_OFFSET 0x00d6
+#define NTB_PPD_OFFSET 0x00d4
+#define XEON_PPD_CONN_TYPE 0x0003
+#define XEON_PPD_DEV_TYPE 0x0010
+#define XEON_PPD_SPLIT_BAR 0x0040
+#define ATOM_PPD_INIT_LINK 0x0008
+#define ATOM_PPD_CONN_TYPE 0x0300
+#define ATOM_PPD_DEV_TYPE 0x1000
+
+/* All addresses are in low 32-bit space so 32-bit BARs can function */
+#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
+#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
+#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
+#define XEON_B2B_BAR4_ADDR32 0x20000000ull
+#define XEON_B2B_BAR5_ADDR32 0x40000000ull
+
+/* The peer ntb secondary config space is 32KB fixed size */
+#define XEON_B2B_MIN_SIZE 0x8000
+
+#endif /* _NTB_REGS_H_ */
Added: head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c Wed Aug 30 21:16:32 2017 (r323032)
@@ -0,0 +1,945 @@
+/*-
+ * Copyright (c) 2017 Alexander Motin <mav at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * The Non-Transparent Bridge (NTB) is a device that allows you to connect
+ * two or more systems using a PCI-e links, providing remote memory access.
+ *
+ * This module contains a driver for NTBs in PLX/Avago/Broadcom PCIe bridges.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+#include <machine/resource.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include "../ntb.h"
+
+#define PLX_MAX_BARS 4 /* There are at most 4 data BARs. */
+#define PLX_NUM_SPAD 8 /* There are 8 scratchpads. */
+#define PLX_NUM_SPAD_PATT 4 /* Use test pattern as 4 more. */
+#define PLX_NUM_DB 16 /* There are 16 doorbells. */
+
+struct ntb_plx_mw_info {
+ int mw_bar;
+ int mw_64bit;
+ int mw_rid;
+ struct resource *mw_res;
+ vm_paddr_t mw_pbase;
+ caddr_t mw_vbase;
+ vm_size_t mw_size;
+ vm_memattr_t mw_map_mode;
+ bus_addr_t mw_xlat_addr;
+ size_t mw_xlat_size;
+};
+
+struct ntb_plx_softc {
+ /* ntb.c context. Do not move! Must go first! */
+ void *ntb_store;
+
+ device_t dev;
+ struct resource *conf_res;
+ int conf_rid;
+ u_int ntx; /* NTx number within chip. */
+ u_int link; /* Link v/s Virtual side. */
+ u_int port; /* Port number within chip. */
+
+ int int_rid;
+ struct resource *int_res;
+ void *int_tag;
+
+ struct ntb_plx_mw_info mw_info[PLX_MAX_BARS];
+ int mw_count; /* Number of memory windows. */
+
+ int spad_count1; /* Number of standard spads. */
+ int spad_count2; /* Number of extra spads. */
+ uint32_t spad_off1; /* Offset of our spads. */
+ uint32_t spad_off2; /* Offset of our extra spads. */
+ uint32_t spad_offp1; /* Offset of peer spads. */
+ uint32_t spad_offp2; /* Offset of peer extra spads. */
+
+ /* Parameters of window shared with peer config access in B2B mode. */
+ int b2b_mw; /* Shared window number. */
+ uint64_t b2b_off; /* Offset in shared window. */
+};
+
+#define PLX_NT0_BASE 0x3E000
+#define PLX_NT1_BASE 0x3C000
+#define PLX_NTX_BASE(sc) ((sc)->ntx ? PLX_NT1_BASE : PLX_NT0_BASE)
+#define PLX_NTX_LINK_OFFSET 0x01000
+
+/* Bases of NTx our/peer interface registers */
+#define PLX_NTX_OUR(sc) \
+ (PLX_NTX_BASE(sc) + ((sc)->link ? PLX_NTX_LINK_OFFSET : 0))
+#define PLX_NTX_PEER(sc) \
+ (PLX_NTX_BASE(sc) + ((sc)->link ? 0 : PLX_NTX_LINK_OFFSET))
+
+/* Read/write NTx our interface registers */
+#define NTX_READ(sc, reg) \
+ bus_read_4((sc)->conf_res, PLX_NTX_OUR(sc) + (reg))
+#define NTX_WRITE(sc, reg, val) \
+ bus_write_4((sc)->conf_res, PLX_NTX_OUR(sc) + (reg), (val))
+
+/* Read/write NTx peer interface registers */
+#define PNTX_READ(sc, reg) \
+ bus_read_4((sc)->conf_res, PLX_NTX_PEER(sc) + (reg))
+#define PNTX_WRITE(sc, reg, val) \
+ bus_write_4((sc)->conf_res, PLX_NTX_PEER(sc) + (reg), (val))
+
+/* Read/write B2B NTx registers */
+#define BNTX_READ(sc, reg) \
+ bus_read_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \
+ PLX_NTX_BASE(sc) + (reg))
+#define BNTX_WRITE(sc, reg, val) \
+ bus_write_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \
+ PLX_NTX_BASE(sc) + (reg), (val))
+
+static int ntb_plx_init(device_t dev);
+static int ntb_plx_detach(device_t dev);
+static int ntb_plx_mw_set_trans_internal(device_t dev, unsigned mw_idx);
+
+static int
+ntb_plx_probe(device_t dev)
+{
+
+ switch (pci_get_devid(dev)) {
+ case 0x87a010b5:
+ device_set_desc(dev, "PLX Non-Transparent Bridge NT0 Link");
+ return (BUS_PROBE_DEFAULT);
+ case 0x87a110b5:
+ device_set_desc(dev, "PLX Non-Transparent Bridge NT1 Link");
+ return (BUS_PROBE_DEFAULT);
+ case 0x87b010b5:
+ device_set_desc(dev, "PLX Non-Transparent Bridge NT0 Virtual");
+ return (BUS_PROBE_DEFAULT);
+ case 0x87b110b5:
+ device_set_desc(dev, "PLX Non-Transparent Bridge NT1 Virtual");
+ return (BUS_PROBE_DEFAULT);
+ }
+ return (ENXIO);
+}
+
+static int
+ntb_plx_init(device_t dev)
+{
+ struct ntb_plx_softc *sc = device_get_softc(dev);
+ struct ntb_plx_mw_info *mw;
+ uint64_t val64;
+ int i;
+ uint32_t val;
+
+ if (sc->b2b_mw >= 0) {
+ /* Set peer BAR0/1 size and address for B2B NTx access. */
+ mw = &sc->mw_info[sc->b2b_mw];
+ if (mw->mw_64bit) {
+ PNTX_WRITE(sc, 0xe4, 0x3); /* 64-bit */
+ val64 = 0x2000000000000000 * mw->mw_bar | 0x4;
+ PNTX_WRITE(sc, PCIR_BAR(0), val64);
+ PNTX_WRITE(sc, PCIR_BAR(0) + 4, val64 >> 32);
+ } else {
+ PNTX_WRITE(sc, 0xe4, 0x2); /* 32-bit */
+ val = 0x20000000 * mw->mw_bar;
+ PNTX_WRITE(sc, PCIR_BAR(0), val);
+ }
+
+ /* Set Virtual to Link address translation for B2B. */
+ for (i = 0; i < sc->mw_count; i++) {
+ mw = &sc->mw_info[i];
+ if (mw->mw_64bit) {
+ val64 = 0x2000000000000000 * mw->mw_bar;
+ NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, val64);
+ NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4 + 4, val64 >> 32);
+ } else {
+ val = 0x20000000 * mw->mw_bar;
+ NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, val);
+ }
+ }
+
+ /* Enable Link Interface LUT entry 0 for 0:0.0. */
+ PNTX_WRITE(sc, 0xdb4, 1);
+ }
+
+ /*
+ * Enable Virtual Interface LUT entry 0 for 0:0.0 and
+ * entry 1 for our Requester ID reported by chip.
+ */
+ val = (NTX_READ(sc, 0xc90) << 16) | 0x00010001;
+ NTX_WRITE(sc, sc->link ? 0xdb4 : 0xd94, val);
+
+ /* Set Link to Virtual address translation. */
+ for (i = 0; i < sc->mw_count; i++) {
+ mw = &sc->mw_info[i];
+ if (mw->mw_xlat_size != 0)
+ ntb_plx_mw_set_trans_internal(dev, i);
+ }
+
+ pci_enable_busmaster(dev);
+ if (sc->b2b_mw >= 0)
+ PNTX_WRITE(sc, PCIR_COMMAND, PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+
+ return (0);
+}
+
+static void
+ntb_plx_isr(void *arg)
+{
+ device_t dev = arg;
+ struct ntb_plx_softc *sc = device_get_softc(dev);
+ uint32_t val;
+
+ ntb_db_event((device_t)arg, 0);
+
+ val = NTX_READ(sc, 0xfe0);
+ if (val == 0)
+ return;
+ NTX_WRITE(sc, 0xfe0, val);
+ if (val & 1)
+ device_printf(dev, "Correctable Error\n");
+ if (val & 2)
+ device_printf(dev, "Uncorrectable Error\n");
+ if (val & 4) {
+ /* DL_Down resets link side registers, have to reinit. */
+ ntb_plx_init(dev);
+ ntb_link_event(dev);
+ }
+ if (val & 8)
+ device_printf(dev, "Uncorrectable Error Message Drop\n");
+}
+
+static int
+ntb_plx_setup_intr(device_t dev)
+{
+ struct ntb_plx_softc *sc = device_get_softc(dev);
+ int error;
+
+ /*
+ * XXX: This hardware supports MSI, but I found it unusable.
+ * It generates new MSI only when doorbell register goes from
+ * zero, but does not generate it when another bit is set or on
+ * partial clear. It makes operation very racy and unreliable.
+ * The data book mentions some mask juggling magic to workaround
+ * that, but I failed to make it work.
+ */
+ sc->int_rid = 0;
+ sc->int_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ &sc->int_rid, RF_SHAREABLE|RF_ACTIVE);
+ if (sc->int_res == NULL) {
+ device_printf(dev, "bus_alloc_resource failed\n");
+ return (ENOMEM);
+ }
+ error = bus_setup_intr(dev, sc->int_res, INTR_MPSAFE | INTR_TYPE_MISC,
+ NULL, ntb_plx_isr, dev, &sc->int_tag);
+ if (error != 0) {
+ device_printf(dev, "bus_setup_intr failed: %d\n", error);
+ return (error);
+ }
+ NTX_WRITE(sc, 0xfe0, 0xf); /* Clear link interrupts. */
+ NTX_WRITE(sc, 0xfe4, 0x0); /* Unmask link interrupts. */
+ return (0);
+}
+
+static void
+ntb_plx_teardown_intr(device_t dev)
+{
+ struct ntb_plx_softc *sc = device_get_softc(dev);
+
+ NTX_WRITE(sc, 0xfe4, 0xf); /* Mask link interrupts. */
+ if (sc->int_res) {
+ bus_teardown_intr(dev, sc->int_res, sc->int_tag);
+ bus_release_resource(dev, SYS_RES_IRQ, sc->int_rid,
+ sc->int_res);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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