svn commit: r305621 - in head/sys/mips: cavium gxemul include mips nlm rmi sibyte
Ruslan Bukin
br at FreeBSD.org
Thu Sep 8 17:37:15 UTC 2016
Author: br
Date: Thu Sep 8 17:37:13 2016
New Revision: 305621
URL: https://svnweb.freebsd.org/changeset/base/305621
Log:
Allow the use of soft-interrupts for sending IPIs.
This will be required for SMP support on MIPS Malta platform.
Reviewed by: adrian
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D7835
Modified:
head/sys/mips/cavium/octeon_mp.c
head/sys/mips/gxemul/gxemul_machdep.c
head/sys/mips/include/hwfunc.h
head/sys/mips/mips/mp_machdep.c
head/sys/mips/nlm/xlp_machdep.c
head/sys/mips/rmi/xlr_machdep.c
head/sys/mips/sibyte/sb_machdep.c
head/sys/mips/sibyte/sb_scd.c
Modified: head/sys/mips/cavium/octeon_mp.c
==============================================================================
--- head/sys/mips/cavium/octeon_mp.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/cavium/octeon_mp.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -63,11 +63,19 @@ platform_ipi_clear(void)
}
int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
{
+
return (1);
}
+int
+platform_ipi_softintr_num(void)
+{
+
+ return (-1);
+}
+
void
platform_init_ap(int cpuid)
{
@@ -93,7 +101,7 @@ platform_init_ap(int cpuid)
*/
ciu_int_mask = hard_int_mask(0);
clock_int_mask = hard_int_mask(5);
- ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+ ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
mips_wbflush();
Modified: head/sys/mips/gxemul/gxemul_machdep.c
==============================================================================
--- head/sys/mips/gxemul/gxemul_machdep.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/gxemul/gxemul_machdep.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -186,11 +186,19 @@ platform_ipi_clear(void)
}
int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
{
+
return (GXEMUL_MP_DEV_IPI_INTERRUPT - 2);
}
+int
+platform_ipi_softintr_num(void)
+{
+
+ return (-1);
+}
+
struct cpu_group *
platform_smp_topo(void)
{
@@ -206,7 +214,7 @@ platform_init_ap(int cpuid)
* Unmask the clock and ipi interrupts.
*/
clock_int_mask = hard_int_mask(5);
- ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+ ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
set_intr_mask(ipi_int_mask | clock_int_mask);
}
Modified: head/sys/mips/include/hwfunc.h
==============================================================================
--- head/sys/mips/include/hwfunc.h Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/include/hwfunc.h Thu Sep 8 17:37:13 2016 (r305621)
@@ -67,7 +67,8 @@ void platform_init_ap(int processor_id);
* This hardware interrupt is used to deliver IPIs exclusively and must
* not be used for any other interrupt source.
*/
-int platform_ipi_intrnum(void);
+int platform_ipi_hardintr_num(void);
+int platform_ipi_softintr_num(void);
/*
* Trigger a IPI interrupt on 'cpuid'.
Modified: head/sys/mips/mips/mp_machdep.c
==============================================================================
--- head/sys/mips/mips/mp_machdep.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/mips/mp_machdep.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -345,9 +345,15 @@ release_aps(void *dummy __unused)
/*
* IPI handler
*/
- ipi_irq = platform_ipi_intrnum();
- cpu_establish_hardintr("ipi", mips_ipi_handler, NULL, NULL, ipi_irq,
- INTR_TYPE_MISC | INTR_EXCL, NULL);
+ ipi_irq = platform_ipi_hardintr_num();
+ if (ipi_irq != -1) {
+ cpu_establish_hardintr("ipi", mips_ipi_handler, NULL, NULL,
+ ipi_irq, INTR_TYPE_MISC | INTR_EXCL, NULL);
+ } else {
+ ipi_irq = platform_ipi_softintr_num();
+ cpu_establish_softintr("ipi", mips_ipi_handler, NULL, NULL,
+ ipi_irq, INTR_TYPE_MISC | INTR_EXCL, NULL);
+ }
atomic_store_rel_int(&aps_ready, 1);
Modified: head/sys/mips/nlm/xlp_machdep.c
==============================================================================
--- head/sys/mips/nlm/xlp_machdep.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/nlm/xlp_machdep.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -687,18 +687,25 @@ platform_init_ap(int cpuid)
}
int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
{
return (IRQ_IPI);
}
+int
+platform_ipi_softintr_num(void)
+{
+
+ return (-1);
+}
+
void
platform_ipi_send(int cpuid)
{
nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid],
- platform_ipi_intrnum(), 0);
+ platform_ipi_hardintr_num(), 0);
}
void
Modified: head/sys/mips/rmi/xlr_machdep.c
==============================================================================
--- head/sys/mips/rmi/xlr_machdep.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/rmi/xlr_machdep.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -571,17 +571,24 @@ platform_init_ap(int cpuid)
}
int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
{
return (IRQ_IPI);
}
+int
+platform_ipi_softintr_num(void)
+{
+
+ return (-1);
+}
+
void
platform_ipi_send(int cpuid)
{
- pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_intrnum());
+ pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_hardintr_num());
}
void
Modified: head/sys/mips/sibyte/sb_machdep.c
==============================================================================
--- head/sys/mips/sibyte/sb_machdep.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/sibyte/sb_machdep.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -124,7 +124,7 @@ sb_intr_init(int cpuid)
* with any other interrupt source.
*/
if (intsrc == INTSRC_MAILBOX3) {
- intrnum = platform_ipi_intrnum();
+ intrnum = platform_ipi_hardintr_num();
sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
}
@@ -313,12 +313,19 @@ platform_ipi_clear(void)
}
int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
{
return (4);
}
+int
+platform_ipi_softintr_num(void)
+{
+
+ return (-1);
+}
+
struct cpu_group *
platform_smp_topo(void)
{
@@ -344,7 +351,7 @@ platform_init_ap(int cpuid)
* Unmask the clock and ipi interrupts.
*/
clock_int_mask = hard_int_mask(5);
- ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+ ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
set_intr_mask(ipi_int_mask | clock_int_mask);
}
Modified: head/sys/mips/sibyte/sb_scd.c
==============================================================================
--- head/sys/mips/sibyte/sb_scd.c Thu Sep 8 15:53:49 2016 (r305620)
+++ head/sys/mips/sibyte/sb_scd.c Thu Sep 8 17:37:13 2016 (r305621)
@@ -207,7 +207,7 @@ sb_route_intsrc(int intsrc)
* Use a deterministic mapping for the remaining sources.
*/
#ifdef SMP
- KASSERT(platform_ipi_intrnum() == 4,
+ KASSERT(platform_ipi_hardintr_num() == 4,
("Unexpected interrupt number used for IPI"));
intrnum = intsrc % 4;
#else
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