svn commit: r300125 - head/sys/dev/siba
Adrian Chadd
adrian at FreeBSD.org
Wed May 18 07:01:24 UTC 2016
Author: adrian
Date: Wed May 18 07:01:22 2016
New Revision: 300125
URL: https://svnweb.freebsd.org/changeset/base/300125
Log:
[siba] use the correct SPROM offsets.
I transcribed the linux ssb offsets and .. didn't pick up that our SIBA
SPROM code has an offset of 0x1000.
This fixes a bunch of odd parsing values that showed up when I tried
using a newer NIC. The NIC still doesn't yet work but now the SPROM
values are right.
Oops!
Modified:
head/sys/dev/siba/sibareg.h
Modified: head/sys/dev/siba/sibareg.h
==============================================================================
--- head/sys/dev/siba/sibareg.h Wed May 18 06:52:20 2016 (r300124)
+++ head/sys/dev/siba/sibareg.h Wed May 18 07:01:22 2016 (r300125)
@@ -399,10 +399,10 @@
#define SIBA_SPROM4_GPIOB_P3 0xff00
/* The following four blocks share the same structure */
-#define SIBA_SPROM4_PWR_INFO_CORE0 0x0080
-#define SIBA_SPROM4_PWR_INFO_CORE1 0x00AE
-#define SIBA_SPROM4_PWR_INFO_CORE2 0x00DC
-#define SIBA_SPROM4_PWR_INFO_CORE3 0x010A
+#define SIBA_SPROM4_PWR_INFO_CORE0 0x1080
+#define SIBA_SPROM4_PWR_INFO_CORE1 0x10AE
+#define SIBA_SPROM4_PWR_INFO_CORE2 0x10DC
+#define SIBA_SPROM4_PWR_INFO_CORE3 0x110A
#define SIBA_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */
#define SIBA_SPROM4_2G_MAXP 0x00FF
@@ -486,8 +486,8 @@
#define SIBA_SPROM8_RXPO5G 0xff00
/* The FEM blocks share the same structure */
-#define SIBA_SPROM8_FEM2G 0x00AE
-#define SIBA_SPROM8_FEM5G 0x00B0
+#define SIBA_SPROM8_FEM2G 0x10ae
+#define SIBA_SPROM8_FEM5G 0x10b0
#define SSB_SROM8_FEM_TSSIPOS 0x0001
#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
@@ -526,10 +526,10 @@
#define SIBA_SPROM8_BWDUPPO 0x0198
/* There are 4 blocks with power info sharing the same layout */
-#define SIBA_SROM8_PWR_INFO_CORE0 0x00C0
-#define SIBA_SROM8_PWR_INFO_CORE1 0x00E0
-#define SIBA_SROM8_PWR_INFO_CORE2 0x0100
-#define SIBA_SROM8_PWR_INFO_CORE3 0x0120
+#define SIBA_SROM8_PWR_INFO_CORE0 0x10C0
+#define SIBA_SROM8_PWR_INFO_CORE1 0x10E0
+#define SIBA_SROM8_PWR_INFO_CORE2 0x1100
+#define SIBA_SROM8_PWR_INFO_CORE3 0x1120
#define SIBA_SROM8_2G_MAXP_ITSSI 0x00
#define SIBA_SPROM8_2G_MAXP 0x00FF
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