svn commit: r299135 - head/sys/dev/bhnd/bhndb
Adrian Chadd
adrian at FreeBSD.org
Thu May 5 19:56:20 UTC 2016
Author: adrian
Date: Thu May 5 19:56:18 2016
New Revision: 299135
URL: https://svnweb.freebsd.org/changeset/base/299135
Log:
[bhnd] don't use anonymous unions.
Found by: gcc-4.2
Modified:
head/sys/dev/bhnd/bhndb/bhndb.c
head/sys/dev/bhnd/bhndb/bhndb.h
head/sys/dev/bhnd/bhndb/bhndb_pci.c
head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
head/sys/dev/bhnd/bhndb/bhndb_subr.c
Modified: head/sys/dev/bhnd/bhndb/bhndb.c
==============================================================================
--- head/sys/dev/bhnd/bhndb/bhndb.c Thu May 5 19:55:16 2016 (r299134)
+++ head/sys/dev/bhnd/bhndb/bhndb.c Thu May 5 19:56:18 2016 (r299135)
@@ -259,9 +259,9 @@ bhndb_initialize_region_cfg(struct bhndb
continue;
/* Fetch the base address of the mapped port. */
- error = bhnd_get_region_addr(child,
- regw->core.port_type, regw->core.port,
- regw->core.region, &addr, &size);
+ error = bhnd_get_region_addr(child,
+ regw->d.core.port_type, regw->d.core.port,
+ regw->d.core.region, &addr, &size);
if (error)
return (error);
Modified: head/sys/dev/bhnd/bhndb/bhndb.h
==============================================================================
--- head/sys/dev/bhnd/bhndb/bhndb.h Thu May 5 19:55:16 2016 (r299134)
+++ head/sys/dev/bhnd/bhndb/bhndb.h Thu May 5 19:56:18 2016 (r299135)
@@ -98,7 +98,7 @@ struct bhndb_regwin {
struct {
bus_size_t cfg_offset; /**< window address config offset. */
} dyn;
- };
+ } d;
};
#define BHNDB_REGWIN_TABLE_END { BHNDB_REGWIN_T_INVALID, 0, 0, { 0, 0 } }
@@ -170,4 +170,4 @@ struct bhndb_hw_priority {
#define BHNDB_HW_PRIORITY_TABLE_END { {}, BHNDB_PRIORITY_NONE, NULL, 0 }
-#endif /* _BHND_BHNDB_H_ */
\ No newline at end of file
+#endif /* _BHND_BHNDB_H_ */
Modified: head/sys/dev/bhnd/bhndb/bhndb_pci.c
==============================================================================
--- head/sys/dev/bhnd/bhndb/bhndb_pci.c Thu May 5 19:55:16 2016 (r299134)
+++ head/sys/dev/bhnd/bhndb/bhndb_pci.c Thu May 5 19:56:18 2016 (r299135)
@@ -313,7 +313,7 @@ bhndb_pci_compat_setregwin(struct bhndb_
if ((error = bhndb_pci_fast_setregwin(sc, rw, addr)))
return (error);
- if (pci_read_config(parent, rw->dyn.cfg_offset, 4) == addr)
+ if (pci_read_config(parent, rw->d.dyn.cfg_offset, 4) == addr)
return (0);
DELAY(10);
@@ -343,7 +343,7 @@ bhndb_pci_fast_setregwin(struct bhndb_pc
if (addr % rw->win_size != 0)
return (EINVAL);
- pci_write_config(parent, rw->dyn.cfg_offset, addr, 4);
+ pci_write_config(parent, rw->d.dyn.cfg_offset, addr, 4);
break;
default:
return (ENODEV);
Modified: head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
==============================================================================
--- head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c Thu May 5 19:55:16 2016 (r299134)
+++ head/sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c Thu May 5 19:56:18 2016 (r299135)
@@ -93,7 +93,9 @@ const struct bhndb_hwcfg bhndb_pci_siba_
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
BHNDB_REGWIN_TABLE_END
@@ -122,7 +124,9 @@ const struct bhndb_hwcfg bhndb_pci_bcma_
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -131,7 +135,7 @@ const struct bhndb_hwcfg bhndb_pci_bcma_
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_CC,
.unit = 0,
.port = 0,
@@ -327,7 +331,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -344,7 +350,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_PCI,
.unit = 0,
.port = 0,
@@ -375,7 +381,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -392,7 +400,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_PCI,
.unit = 0,
.port = 0,
@@ -407,7 +415,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_CC,
.unit = 0,
.port = 0,
@@ -439,7 +447,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -456,7 +466,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_PCIE,
.unit = 0,
.port = 0,
@@ -471,7 +481,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_CC,
.unit = 0,
.port = 0,
@@ -503,7 +513,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -512,7 +524,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -521,7 +535,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_PCIE,
.unit = 0,
.port = 0,
@@ -536,7 +550,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_CC,
.unit = 0,
.port = 0,
@@ -568,7 +582,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -577,7 +593,9 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE,
- .dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
+ .d.dyn = {
+ .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
+ },
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
},
@@ -586,7 +604,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_PCIE,
.unit = 0,
.port = 0,
@@ -601,7 +619,7 @@ static const struct bhndb_hwcfg bhndb_pc
.win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE,
- .core = {
+ .d.core = {
.class = BHND_DEVCLASS_CC,
.unit = 0,
.port = 0,
Modified: head/sys/dev/bhnd/bhndb/bhndb_subr.c
==============================================================================
--- head/sys/dev/bhnd/bhndb/bhndb_subr.c Thu May 5 19:55:16 2016 (r299134)
+++ head/sys/dev/bhnd/bhndb/bhndb_subr.c Thu May 5 19:56:18 2016 (r299135)
@@ -873,19 +873,19 @@ bhndb_regwin_find_core(const struct bhnd
if (rw->win_type != BHNDB_REGWIN_T_CORE)
continue;
- if (rw->core.class != class)
+ if (rw->d.core.class != class)
continue;
- if (unit != -1 && rw->core.unit != unit)
+ if (unit != -1 && rw->d.core.unit != unit)
continue;
- if (rw->core.port_type != port_type)
+ if (rw->d.core.port_type != port_type)
continue;
- if (rw->core.port != port)
+ if (rw->d.core.port != port)
continue;
- if (rw->core.region != region)
+ if (rw->d.core.region != region)
continue;
return (rw);
@@ -944,16 +944,16 @@ bhndb_regwin_matches_device(const struct
return (false);
/* Device class must match */
- if (bhnd_get_class(dev) != regw->core.class)
+ if (bhnd_get_class(dev) != regw->d.core.class)
return (false);
/* Device unit must match */
- if (bhnd_get_core_unit(dev) != regw->core.unit)
+ if (bhnd_get_core_unit(dev) != regw->d.core.unit)
return (false);
/* The regwin port/region must be defined. */
- if (!bhnd_is_region_valid(dev, regw->core.port_type, regw->core.port,
- regw->core.region))
+ if (!bhnd_is_region_valid(dev, regw->d.core.port_type, regw->d.core.port,
+ regw->d.core.region))
{
return (false);
}
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