svn commit: r295150 - head/sys/mips/include

[Adrian Chadd]

Author: adrian
Date: Tue Feb  2 16:00:42 2016
New Revision: 295150
URL: https://svnweb.freebsd.org/changeset/base/295150

Log:
  Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for
  clearing hazards.
  
  This revision makes currently known MIPS32 Release 2 and Release 3 CPUs use
  the EHB instruction when clearing hazards. So far the MIPS 74K and MIPS1004K
   (somewhat) were already using the EHB. Now we add more r2 and r3 CPUs to
  this list.
  
  Also, for the cases of MIPS coherent processing systems (currently 1004K,
  1074K, interAptiv and proAptiv) - define proper CCA attributes.
  
  Submitted by:	Stanislav Galabov <sgalabov at gmail.com>
  Reviewed by:	imp
  Differential Revision:	https://reviews.freebsd.org/D5078

Modified:
  head/sys/mips/include/cpuregs.h

Modified: head/sys/mips/include/cpuregs.h
==============================================================================
--- head/sys/mips/include/cpuregs.h	Tue Feb  2 14:53:34 2016	(r295149)
+++ head/sys/mips/include/cpuregs.h	Tue Feb  2 16:00:42 2016	(r295150)
@@ -110,6 +110,7 @@
  *	C:	Cacheable, coherency unspecified.
  *	CNC:	Cacheable non-coherent.
  *	CC:	Cacheable coherent.
+ *	CCS:	Cacheable coherent, shared read.
  *	CCE:	Cacheable coherent, exclusive read.
  *	CCEW:	Cacheable coherent, exclusive write.
  *	CCUOW:	Cacheable coherent, update on write.
@@ -154,9 +155,20 @@
 #define	MIPS_CCA_CACHED		0x03
 #endif
 
-#if defined(CPU_MIPS1004K)
-#define	MIPS_CCA_UNCACHED	0x02
-#define	MIPS_CCA_CACHED		0x05
+/*
+ * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
+ * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
+ * CCA 0x03 and Uncached Accelerated CCA 0x07
+ */
+#if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) ||	\
+    defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
+#define	MIPS_CCA_CNC		0x03
+#define	MIPS_CCA_CCE		0x04
+#define	MIPS_CCA_CCS		0x05
+#define	MIPS_CCA_UA		0x07
+
+/* We use shared read CCA for CACHED CCA */
+#define	MIPS_CCA_CACHED		MIPS_CCA_CCS
 #endif
 
 #ifndef	MIPS_CCA_UNCACHED
@@ -214,8 +226,18 @@
 #define	COP0_SYNC	.word 0xc0	/* ehb */
 #elif defined(CPU_SB1)
 #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
-#elif defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)
-#define	COP0_SYNC	 .word 0xc0	/* ehb */
+#elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) ||		\
+      defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)  ||	\
+      defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) ||	\
+      defined(CPU_PROAPTIV)
+/*
+ * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00:
+ * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be
+ *  removed, leaving only the EHB".
+ * Also, all MIPS32 Release 2 implementations have the EHB instruction, which
+ * resolves all execution hazards. The same goes for MIPS32 Release 3.
+ */
+#define	COP0_SYNC	.word 0xc0	/* ehb */
 #else
 /*
  * Pick a reasonable default based on the "typical" spacing described in the