svn commit: r304338 - stable/10/sys/dev/e1000
Sean Bruno
sbruno at FreeBSD.org
Thu Aug 18 07:32:05 UTC 2016
Author: sbruno
Date: Thu Aug 18 07:32:02 2016
New Revision: 304338
URL: https://svnweb.freebsd.org/changeset/base/304338
Log:
MFC r304149
e1000: Add support for Kaby Lake IDs
Fixup some errors when transitioning to/from low power states.
Modified:
stable/10/sys/dev/e1000/e1000_api.c
stable/10/sys/dev/e1000/e1000_hw.h
stable/10/sys/dev/e1000/e1000_ich8lan.c
stable/10/sys/dev/e1000/e1000_ich8lan.h
stable/10/sys/dev/e1000/e1000_phy.c
stable/10/sys/dev/e1000/if_em.c
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/sys/dev/e1000/e1000_api.c
==============================================================================
--- stable/10/sys/dev/e1000/e1000_api.c Thu Aug 18 07:31:19 2016 (r304337)
+++ stable/10/sys/dev/e1000/e1000_api.c Thu Aug 18 07:32:02 2016 (r304338)
@@ -304,6 +304,10 @@ s32 e1000_set_mac_type(struct e1000_hw *
case E1000_DEV_ID_PCH_SPT_I219_LM2:
case E1000_DEV_ID_PCH_SPT_I219_V2:
case E1000_DEV_ID_PCH_LBG_I219_LM3:
+ case E1000_DEV_ID_PCH_SPT_I219_LM4:
+ case E1000_DEV_ID_PCH_SPT_I219_V4:
+ case E1000_DEV_ID_PCH_SPT_I219_LM5:
+ case E1000_DEV_ID_PCH_SPT_I219_V5:
mac->type = e1000_pch_spt;
break;
case E1000_DEV_ID_82575EB_COPPER:
Modified: stable/10/sys/dev/e1000/e1000_hw.h
==============================================================================
--- stable/10/sys/dev/e1000/e1000_hw.h Thu Aug 18 07:31:19 2016 (r304337)
+++ stable/10/sys/dev/e1000/e1000_hw.h Thu Aug 18 07:32:02 2016 (r304338)
@@ -142,6 +142,10 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
+#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
+#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
+#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
+#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
#define E1000_DEV_ID_82576 0x10C9
#define E1000_DEV_ID_82576_FIBER 0x10E6
#define E1000_DEV_ID_82576_SERDES 0x10E7
@@ -957,9 +961,13 @@ struct e1000_dev_spec_ich8lan {
E1000_MUTEX nvm_mutex;
E1000_MUTEX swflag_mutex;
bool nvm_k1_enabled;
+ bool disable_k1_off;
bool eee_disable;
u16 eee_lp_ability;
enum e1000_ulp_state ulp_state;
+ bool ulp_capability_disabled;
+ bool during_suspend_flow;
+ bool during_dpg_exit;
};
struct e1000_dev_spec_82575 {
Modified: stable/10/sys/dev/e1000/e1000_ich8lan.c
==============================================================================
--- stable/10/sys/dev/e1000/e1000_ich8lan.c Thu Aug 18 07:31:19 2016 (r304337)
+++ stable/10/sys/dev/e1000/e1000_ich8lan.c Thu Aug 18 07:32:02 2016 (r304338)
@@ -288,7 +288,7 @@ static void e1000_toggle_lanphypc_pch_lp
mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
E1000_WRITE_FLUSH(hw);
- usec_delay(10);
+ msec_delay(1);
mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
E1000_WRITE_FLUSH(hw);
@@ -1625,7 +1625,17 @@ static s32 e1000_check_for_copper_link_i
hw->phy.ops.write_reg_locked(hw,
I217_PLL_CLOCK_GATE_REG,
phy_reg);
- }
+
+ if (speed == SPEED_1000) {
+ hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
+ &phy_reg);
+
+ phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
+
+ hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
+ phy_reg);
+ }
+ }
hw->phy.ops.release(hw);
if (ret_val)
@@ -1718,7 +1728,8 @@ static s32 e1000_check_for_copper_link_i
u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
- if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
+ if ((pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) &&
+ (hw->dev_spec.ich8lan.disable_k1_off == FALSE))
fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
else
fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
Modified: stable/10/sys/dev/e1000/e1000_ich8lan.h
==============================================================================
--- stable/10/sys/dev/e1000/e1000_ich8lan.h Thu Aug 18 07:31:19 2016 (r304337)
+++ stable/10/sys/dev/e1000/e1000_ich8lan.h Thu Aug 18 07:32:02 2016 (r304338)
@@ -239,7 +239,7 @@
/* PHY Power Management Control */
#define HV_PM_CTRL PHY_REG(770, 17)
-#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
+#define HV_PM_CTRL_K1_CLK_REQ 0x200
#define HV_PM_CTRL_K1_ENABLE 0x4000
#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
Modified: stable/10/sys/dev/e1000/e1000_phy.c
==============================================================================
--- stable/10/sys/dev/e1000/e1000_phy.c Thu Aug 18 07:31:19 2016 (r304337)
+++ stable/10/sys/dev/e1000/e1000_phy.c Thu Aug 18 07:32:02 2016 (r304338)
@@ -4148,10 +4148,10 @@ s32 e1000_read_phy_reg_mphy(struct e1000
/* Disable access to mPHY if it was originally disabled */
if (locked)
ready = e1000_is_mphy_ready(hw);
- if (!ready)
- return -E1000_ERR_PHY;
- E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
- E1000_MPHY_DIS_ACCESS);
+ if (!ready)
+ return -E1000_ERR_PHY;
+ E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
+ E1000_MPHY_DIS_ACCESS);
return E1000_SUCCESS;
}
@@ -4213,10 +4213,10 @@ s32 e1000_write_phy_reg_mphy(struct e100
/* Disable access to mPHY if it was originally disabled */
if (locked)
ready = e1000_is_mphy_ready(hw);
- if (!ready)
- return -E1000_ERR_PHY;
- E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
- E1000_MPHY_DIS_ACCESS);
+ if (!ready)
+ return -E1000_ERR_PHY;
+ E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
+ E1000_MPHY_DIS_ACCESS);
return E1000_SUCCESS;
}
Modified: stable/10/sys/dev/e1000/if_em.c
==============================================================================
--- stable/10/sys/dev/e1000/if_em.c Thu Aug 18 07:31:19 2016 (r304337)
+++ stable/10/sys/dev/e1000/if_em.c Thu Aug 18 07:32:02 2016 (r304338)
@@ -192,6 +192,12 @@ static em_vendor_info_t em_vendor_info_a
{ 0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3,
PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4,
+ PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5,
+ PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, PCI_ANY_ID, PCI_ANY_ID, 0},
/* required last entry */
{ 0, 0, 0, 0, 0}
};
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