svn commit: r304298 - in vendor/llvm/dist: . cmake/modules docs docs/CommandGuide docs/TableGen include/llvm-c include/llvm/ADT include/llvm/Analysis include/llvm/CodeGen include/llvm/IR include/ll...
Dimitry Andric
dim at FreeBSD.org
Wed Aug 17 19:33:55 UTC 2016
Author: dim
Date: Wed Aug 17 19:33:52 2016
New Revision: 304298
URL: https://svnweb.freebsd.org/changeset/base/304298
Log:
Vendor import of llvm release_39 branch r278877:
https://llvm.org/svn/llvm-project/llvm/branches/release_39@278877
Added:
vendor/llvm/dist/lib/IR/AttributeSetNode.h (contents, props changed)
vendor/llvm/dist/test/CodeGen/AArch64/aarch64-vcvtfp2fxs-combine.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/invalid-opencl-version-metadata1.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/invalid-opencl-version-metadata2.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/invalid-opencl-version-metadata3.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
vendor/llvm/dist/test/CodeGen/ARM/ssat-v4t.ll
vendor/llvm/dist/test/CodeGen/ARM/usat-v4t.ll
vendor/llvm/dist/test/CodeGen/Mips/jumptable_labels.ll
vendor/llvm/dist/test/CodeGen/X86/pr28504.ll
vendor/llvm/dist/test/CodeGen/X86/pr28824.ll
vendor/llvm/dist/test/CodeGen/X86/tail-merge-after-mbp.ll
vendor/llvm/dist/test/DebugInfo/COFF/pr28747.ll
vendor/llvm/dist/test/Linker/Inputs/metadata-with-global-value-operand.ll
vendor/llvm/dist/test/Linker/metadata-with-global-value-operand.ll
vendor/llvm/dist/test/Transforms/IndVarSimplify/pr28935.ll
vendor/llvm/dist/test/Transforms/Inline/inalloca-not-static.ll
vendor/llvm/dist/test/Transforms/LCSSA/pr28424.ll
vendor/llvm/dist/test/Transforms/LCSSA/pr28608.ll
vendor/llvm/dist/test/Transforms/LoopSimplify/pr28272.ll
vendor/llvm/dist/test/Transforms/LoopStrengthReduce/X86/pr28719.ll
vendor/llvm/dist/test/Transforms/LoopVectorize/pr28541.ll
vendor/llvm/dist/test/Transforms/SafeStack/coloring-ssp.ll
vendor/llvm/dist/test/Transforms/SafeStack/layout-region-split.ll
Deleted:
vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticgroup.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/reciprocal.ll
Modified:
vendor/llvm/dist/CMakeLists.txt
vendor/llvm/dist/LICENSE.TXT
vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake
vendor/llvm/dist/docs/CodeGenerator.rst
vendor/llvm/dist/docs/CommandGuide/FileCheck.rst
vendor/llvm/dist/docs/CommandGuide/llvm-nm.rst
vendor/llvm/dist/docs/CommandGuide/opt.rst
vendor/llvm/dist/docs/ExceptionHandling.rst
vendor/llvm/dist/docs/Extensions.rst
vendor/llvm/dist/docs/GarbageCollection.rst
vendor/llvm/dist/docs/GetElementPtr.rst
vendor/llvm/dist/docs/HowToUseInstrMappings.rst
vendor/llvm/dist/docs/InAlloca.rst
vendor/llvm/dist/docs/LangRef.rst
vendor/llvm/dist/docs/MIRLangRef.rst
vendor/llvm/dist/docs/MarkedUpDisassembly.rst
vendor/llvm/dist/docs/MergeFunctions.rst
vendor/llvm/dist/docs/NVPTXUsage.rst
vendor/llvm/dist/docs/ReleaseNotes.rst
vendor/llvm/dist/docs/SegmentedStacks.rst
vendor/llvm/dist/docs/SourceLevelDebugging.rst
vendor/llvm/dist/docs/Statepoints.rst
vendor/llvm/dist/docs/TableGen/LangIntro.rst
vendor/llvm/dist/docs/TableGen/index.rst
vendor/llvm/dist/docs/WritingAnLLVMBackend.rst
vendor/llvm/dist/docs/WritingAnLLVMPass.rst
vendor/llvm/dist/docs/index.rst
vendor/llvm/dist/include/llvm-c/Core.h
vendor/llvm/dist/include/llvm/ADT/GraphTraits.h
vendor/llvm/dist/include/llvm/ADT/SCCIterator.h
vendor/llvm/dist/include/llvm/ADT/STLExtras.h
vendor/llvm/dist/include/llvm/ADT/Triple.h
vendor/llvm/dist/include/llvm/ADT/iterator.h
vendor/llvm/dist/include/llvm/Analysis/CallGraph.h
vendor/llvm/dist/include/llvm/Analysis/ScalarEvolutionExpander.h
vendor/llvm/dist/include/llvm/CodeGen/MachineBasicBlock.h
vendor/llvm/dist/include/llvm/IR/Attributes.h
vendor/llvm/dist/include/llvm/IR/CFG.h
vendor/llvm/dist/include/llvm/IR/IntrinsicsX86.td
vendor/llvm/dist/include/llvm/Target/TargetLowering.h
vendor/llvm/dist/lib/Analysis/BlockFrequencyInfoImpl.cpp
vendor/llvm/dist/lib/Analysis/ConstantFolding.cpp
vendor/llvm/dist/lib/Analysis/InstructionSimplify.cpp
vendor/llvm/dist/lib/Analysis/LoopUnrollAnalyzer.cpp
vendor/llvm/dist/lib/Analysis/ScalarEvolutionExpander.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
vendor/llvm/dist/lib/CodeGen/BranchFolding.cpp
vendor/llvm/dist/lib/CodeGen/SafeStack.cpp
vendor/llvm/dist/lib/CodeGen/SafeStackColoring.cpp
vendor/llvm/dist/lib/CodeGen/SafeStackLayout.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp
vendor/llvm/dist/lib/CodeGen/TwoAddressInstructionPass.cpp
vendor/llvm/dist/lib/IR/AttributeImpl.h
vendor/llvm/dist/lib/IR/AutoUpgrade.cpp
vendor/llvm/dist/lib/IR/Core.cpp
vendor/llvm/dist/lib/IR/Metadata.cpp
vendor/llvm/dist/lib/Support/Triple.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64.td
vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPU.h
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUInstructions.td
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
vendor/llvm/dist/lib/Target/AMDGPU/R600ISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/R600ISelLowering.h
vendor/llvm/dist/lib/Target/AMDGPU/SIDefines.h
vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.h
vendor/llvm/dist/lib/Target/AMDGPU/SIInstrFormats.td
vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h
vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.td
vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td
vendor/llvm/dist/lib/Target/AMDGPU/SIIntrinsics.td
vendor/llvm/dist/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.h
vendor/llvm/dist/lib/Target/AMDGPU/SIWholeQuadMode.cpp
vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp
vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td
vendor/llvm/dist/lib/Target/ARM/ARMInstrThumb2.td
vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
vendor/llvm/dist/lib/Target/Mips/MipsTargetMachine.cpp
vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp
vendor/llvm/dist/lib/Target/X86/X86InstrInfo.cpp
vendor/llvm/dist/lib/Target/X86/X86InstrInfo.h
vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td
vendor/llvm/dist/lib/Transforms/IPO/FunctionAttrs.cpp
vendor/llvm/dist/lib/Transforms/IPO/GlobalOpt.cpp
vendor/llvm/dist/lib/Transforms/IPO/PassManagerBuilder.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineSelect.cpp
vendor/llvm/dist/lib/Transforms/InstCombine/InstructionCombining.cpp
vendor/llvm/dist/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
vendor/llvm/dist/lib/Transforms/Scalar/ConstantProp.cpp
vendor/llvm/dist/lib/Transforms/Scalar/EarlyCSE.cpp
vendor/llvm/dist/lib/Transforms/Scalar/IndVarSimplify.cpp
vendor/llvm/dist/lib/Transforms/Scalar/JumpThreading.cpp
vendor/llvm/dist/lib/Transforms/Scalar/LICM.cpp
vendor/llvm/dist/lib/Transforms/Scalar/LoopStrengthReduce.cpp
vendor/llvm/dist/lib/Transforms/Utils/CloneFunction.cpp
vendor/llvm/dist/lib/Transforms/Utils/InlineFunction.cpp
vendor/llvm/dist/lib/Transforms/Utils/LCSSA.cpp
vendor/llvm/dist/lib/Transforms/Utils/LoopSimplify.cpp
vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp
vendor/llvm/dist/test/CodeGen/AMDGPU/amdgpu-codegenprepare.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/basic-branch.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/fdiv.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/fp_to_sint.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/fp_to_uint.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/rcp-pattern.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/skip-if-dead.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/vector-alloca.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/wqm.ll
vendor/llvm/dist/test/CodeGen/ARM/arm-and-tst-peephole.ll
vendor/llvm/dist/test/CodeGen/ARM/ssat.ll
vendor/llvm/dist/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
vendor/llvm/dist/test/CodeGen/Mips/2010-07-20-Switch.ll
vendor/llvm/dist/test/CodeGen/Mips/analyzebranch.ll
vendor/llvm/dist/test/CodeGen/Mips/atomic.ll
vendor/llvm/dist/test/CodeGen/Mips/blez_bgez.ll
vendor/llvm/dist/test/CodeGen/Mips/blockaddr.ll
vendor/llvm/dist/test/CodeGen/Mips/ehframe-indirect.ll
vendor/llvm/dist/test/CodeGen/Mips/fcmp.ll
vendor/llvm/dist/test/CodeGen/Mips/fpbr.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/ashr.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/indirectbr.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/lshr.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/select-dbl.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/select-flt.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/select-int.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/shl.ll
vendor/llvm/dist/test/CodeGen/Mips/longbranch.ll
vendor/llvm/dist/test/CodeGen/Mips/msa/basic_operations.ll
vendor/llvm/dist/test/CodeGen/Mips/msa/basic_operations_float.ll
vendor/llvm/dist/test/CodeGen/Mips/octeon.ll
vendor/llvm/dist/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
vendor/llvm/dist/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
vendor/llvm/dist/test/CodeGen/X86/avx-intrinsics-x86.ll
vendor/llvm/dist/test/CodeGen/X86/avx512-cvt.ll
vendor/llvm/dist/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll
vendor/llvm/dist/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
vendor/llvm/dist/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll
vendor/llvm/dist/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
vendor/llvm/dist/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
vendor/llvm/dist/test/CodeGen/X86/sse2-intrinsics-x86.ll
vendor/llvm/dist/test/CodeGen/X86/twoaddr-lea.ll
vendor/llvm/dist/test/DebugInfo/COFF/inlining-same-name.ll
vendor/llvm/dist/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll
vendor/llvm/dist/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt
vendor/llvm/dist/test/MC/Mips/cpsetup.s
vendor/llvm/dist/test/MC/Mips/expansion-jal-sym-pic.s
vendor/llvm/dist/test/MC/Mips/macro-la.s
vendor/llvm/dist/test/MC/Mips/mips3/valid.s
vendor/llvm/dist/test/MC/Mips/mips4/valid.s
vendor/llvm/dist/test/MC/Mips/mips5/valid.s
vendor/llvm/dist/test/MC/Mips/mips64/valid.s
vendor/llvm/dist/test/MC/Mips/mips64r2/valid.s
vendor/llvm/dist/test/MC/Mips/mips64r3/valid.s
vendor/llvm/dist/test/MC/Mips/mips64r5/valid.s
vendor/llvm/dist/test/MC/Mips/relocation.s
vendor/llvm/dist/test/Transforms/ConstProp/calls.ll
vendor/llvm/dist/test/Transforms/EarlyCSE/basic.ll
vendor/llvm/dist/test/Transforms/GlobalOpt/metadata.ll
vendor/llvm/dist/test/Transforms/Inline/inline_constprop.ll
vendor/llvm/dist/test/Transforms/InstCombine/call.ll
vendor/llvm/dist/test/Transforms/InstCombine/log-pow.ll
vendor/llvm/dist/test/Transforms/InstCombine/select.ll
vendor/llvm/dist/unittests/ADT/SCCIteratorTest.cpp
vendor/llvm/dist/unittests/IR/MetadataTest.cpp
vendor/llvm/dist/unittests/Support/IteratorTest.cpp
vendor/llvm/dist/utils/release/test-release.sh
Modified: vendor/llvm/dist/CMakeLists.txt
==============================================================================
--- vendor/llvm/dist/CMakeLists.txt Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/CMakeLists.txt Wed Aug 17 19:33:52 2016 (r304298)
@@ -293,6 +293,7 @@ endif()
option(LLVM_ENABLE_CXX1Y "Compile with C++1y enabled." OFF)
option(LLVM_ENABLE_LIBCXX "Use libc++ if available." OFF)
option(LLVM_ENABLE_LIBCXXABI "Use libc++abi when using libc++." OFF)
+option(LLVM_ENABLE_LLD "Use lld as C and C++ linker." OFF)
option(LLVM_ENABLE_PEDANTIC "Compile with pedantic enabled." ON)
option(LLVM_ENABLE_WERROR "Fail and stop if a warning is triggered." OFF)
Modified: vendor/llvm/dist/LICENSE.TXT
==============================================================================
--- vendor/llvm/dist/LICENSE.TXT Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/LICENSE.TXT Wed Aug 17 19:33:52 2016 (r304298)
@@ -61,8 +61,6 @@ licenses, and/or restrictions:
Program Directory
------- ---------
-Autoconf llvm/autoconf
- llvm/projects/ModuleMaker/autoconf
Google Test llvm/utils/unittest/googletest
OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex}
pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT}
Modified: vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake
==============================================================================
--- vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake Wed Aug 17 19:33:52 2016 (r304298)
@@ -144,6 +144,12 @@ function(add_flag_or_print_warning flag
endif()
endfunction()
+if(LLVM_ENABLE_LLD)
+ check_cxx_compiler_flag("-fuse-ld=lld" CXX_SUPPORTS_LLD)
+ append_if(CXX_SUPPORTS_LLD "-fuse-ld=lld"
+ CMAKE_EXE_LINKER_FLAGS CMAKE_MODULE_LINKER_FLAGS CMAKE_SHARED_LINKER_FLAGS)
+endif()
+
if( LLVM_ENABLE_PIC )
if( XCODE )
# Xcode has -mdynamic-no-pic on by default, which overrides -fPIC. I don't
Modified: vendor/llvm/dist/docs/CodeGenerator.rst
==============================================================================
--- vendor/llvm/dist/docs/CodeGenerator.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/CodeGenerator.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -436,7 +436,7 @@ For example, consider this simple LLVM e
The X86 instruction selector might produce this machine code for the ``div`` and
``ret``:
-.. code-block:: llvm
+.. code-block:: text
;; Start of div
%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
@@ -453,7 +453,7 @@ By the end of code generation, the regis
registers and delete the resultant identity moves producing the following
code:
-.. code-block:: llvm
+.. code-block:: text
;; X is in EAX, Y is in ECX
mov %EAX, %EDX
@@ -965,7 +965,7 @@ target code. For example, consider the
This LLVM code corresponds to a SelectionDAG that looks basically like this:
-.. code-block:: llvm
+.. code-block:: text
(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Modified: vendor/llvm/dist/docs/CommandGuide/FileCheck.rst
==============================================================================
--- vendor/llvm/dist/docs/CommandGuide/FileCheck.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/CommandGuide/FileCheck.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -144,7 +144,7 @@ exists anywhere in the file.
The FileCheck -check-prefix option
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The FileCheck :option:`-check-prefix` option allows multiple test
+The FileCheck `-check-prefix` option allows multiple test
configurations to be driven from one `.ll` file. This is useful in many
circumstances, for example, testing different architectural variants with
:program:`llc`. Here's a simple example:
@@ -303,7 +303,7 @@ be aware that the definition rule can ma
So, for instance, the code below will pass:
-.. code-block:: llvm
+.. code-block:: text
; CHECK-DAG: vmov.32 [[REG2:d[0-9]+]][0]
; CHECK-DAG: vmov.32 [[REG2]][1]
@@ -312,7 +312,7 @@ So, for instance, the code below will pa
While this other code, will not:
-.. code-block:: llvm
+.. code-block:: text
; CHECK-DAG: vmov.32 [[REG2:d[0-9]+]][0]
; CHECK-DAG: vmov.32 [[REG2]][1]
@@ -473,7 +473,7 @@ To match newline characters in regular e
matches output of the form (from llvm-dwarfdump):
-.. code-block:: llvm
+.. code-block:: text
DW_AT_location [DW_FORM_sec_offset] (0x00000233)
DW_AT_name [DW_FORM_strp] ( .debug_str[0x000000c9] = "intd")
Modified: vendor/llvm/dist/docs/CommandGuide/llvm-nm.rst
==============================================================================
--- vendor/llvm/dist/docs/CommandGuide/llvm-nm.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/CommandGuide/llvm-nm.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -68,11 +68,11 @@ OPTIONS
.. option:: -B (default)
- Use BSD output format. Alias for :option:`--format=bsd`.
+ Use BSD output format. Alias for `--format=bsd`.
.. option:: -P
- Use POSIX.2 output format. Alias for :option:`--format=posix`.
+ Use POSIX.2 output format. Alias for `--format=posix`.
.. option:: --debug-syms, -a
Modified: vendor/llvm/dist/docs/CommandGuide/opt.rst
==============================================================================
--- vendor/llvm/dist/docs/CommandGuide/opt.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/CommandGuide/opt.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -12,16 +12,16 @@ DESCRIPTION
The :program:`opt` command is the modular LLVM optimizer and analyzer. It
takes LLVM source files as input, runs the specified optimizations or analyses
on it, and then outputs the optimized file or the analysis results. The
-function of :program:`opt` depends on whether the :option:`-analyze` option is
+function of :program:`opt` depends on whether the `-analyze` option is
given.
-When :option:`-analyze` is specified, :program:`opt` performs various analyses
+When `-analyze` is specified, :program:`opt` performs various analyses
of the input source. It will usually print the results on standard output, but
in a few cases, it will print output to standard error or generate a file with
the analysis output, which is usually done when the output is meant for another
program.
-While :option:`-analyze` is *not* given, :program:`opt` attempts to produce an
+While `-analyze` is *not* given, :program:`opt` attempts to produce an
optimized output file. The optimizations available via :program:`opt` depend
upon what libraries were linked into it as well as any additional libraries
that have been loaded with the :option:`-load` option. Use the :option:`-help`
@@ -68,19 +68,19 @@ OPTIONS
.. option:: -disable-opt
- This option is only meaningful when :option:`-std-link-opts` is given. It
+ This option is only meaningful when `-std-link-opts` is given. It
disables most passes.
.. option:: -strip-debug
This option causes opt to strip debug information from the module before
- applying other optimizations. It is essentially the same as :option:`-strip`
+ applying other optimizations. It is essentially the same as `-strip`
but it ensures that stripping of debug information is done first.
.. option:: -verify-each
This option causes opt to add a verify pass after every pass otherwise
- specified on the command line (including :option:`-verify`). This is useful
+ specified on the command line (including `-verify`). This is useful
for cases where it is suspected that a pass is creating an invalid module but
it is not clear which pass is doing it.
Modified: vendor/llvm/dist/docs/ExceptionHandling.rst
==============================================================================
--- vendor/llvm/dist/docs/ExceptionHandling.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/ExceptionHandling.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -406,7 +406,7 @@ outlined. After the handler is outlined
``llvm.eh.exceptionpointer``
----------------------------
-.. code-block:: llvm
+.. code-block:: text
i8 addrspace(N)* @llvm.eh.padparam.pNi8(token %catchpad)
@@ -427,7 +427,7 @@ backend. Uses of them are generated by
``llvm.eh.sjlj.setjmp``
~~~~~~~~~~~~~~~~~~~~~~~
-.. code-block:: llvm
+.. code-block:: text
i32 @llvm.eh.sjlj.setjmp(i8* %setjmp_buf)
@@ -664,7 +664,7 @@ all of the new IR instructions:
return 0;
}
-.. code-block:: llvm
+.. code-block:: text
define i32 @f() nounwind personality i32 (...)* @__CxxFrameHandler3 {
entry:
@@ -741,7 +741,7 @@ C++ code:
}
}
-.. code-block:: llvm
+.. code-block:: text
define void @f() #0 personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
entry:
Modified: vendor/llvm/dist/docs/Extensions.rst
==============================================================================
--- vendor/llvm/dist/docs/Extensions.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/Extensions.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -43,7 +43,7 @@ The following additional relocation type
corresponds to the COFF relocation types ``IMAGE_REL_I386_DIR32NB`` (32-bit) or
``IMAGE_REL_AMD64_ADDR32NB`` (64-bit).
-.. code-block:: gas
+.. code-block:: text
.text
fun:
Modified: vendor/llvm/dist/docs/GarbageCollection.rst
==============================================================================
--- vendor/llvm/dist/docs/GarbageCollection.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/GarbageCollection.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -204,7 +204,7 @@ IR features is specified by the selected
Specifying GC code generation: ``gc "..."``
-------------------------------------------
-.. code-block:: llvm
+.. code-block:: text
define <returntype> @name(...) gc "name" { ... }
Modified: vendor/llvm/dist/docs/GetElementPtr.rst
==============================================================================
--- vendor/llvm/dist/docs/GetElementPtr.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/GetElementPtr.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -105,7 +105,7 @@ memory, or a global variable.
To make this clear, let's consider a more obtuse example:
-.. code-block:: llvm
+.. code-block:: text
%MyVar = uninitialized global i32
...
@@ -142,7 +142,7 @@ Quick answer: there are no superfluous i
This question arises most often when the GEP instruction is applied to a global
variable which is always a pointer type. For example, consider this:
-.. code-block:: llvm
+.. code-block:: text
%MyStruct = uninitialized global { float*, i32 }
...
@@ -178,7 +178,7 @@ The GetElementPtr instruction dereferenc
memory in any way. That's what the Load and Store instructions are for. GEP is
only involved in the computation of addresses. For example, consider this:
-.. code-block:: llvm
+.. code-block:: text
%MyVar = uninitialized global { [40 x i32 ]* }
...
@@ -195,7 +195,7 @@ illegal.
In order to access the 18th integer in the array, you would need to do the
following:
-.. code-block:: llvm
+.. code-block:: text
%idx = getelementptr { [40 x i32]* }, { [40 x i32]* }* %, i64 0, i32 0
%arr = load [40 x i32]** %idx
@@ -204,7 +204,7 @@ following:
In this case, we have to load the pointer in the structure with a load
instruction before we can index into the array. If the example was changed to:
-.. code-block:: llvm
+.. code-block:: text
%MyVar = uninitialized global { [40 x i32 ] }
...
Modified: vendor/llvm/dist/docs/HowToUseInstrMappings.rst
==============================================================================
--- vendor/llvm/dist/docs/HowToUseInstrMappings.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/HowToUseInstrMappings.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -30,7 +30,7 @@ instructions with each other. These tabl
``XXXInstrInfo.inc`` file along with the functions to query them. Following
is the definition of ``InstrMapping`` class definied in Target.td file:
-.. code-block:: llvm
+.. code-block:: text
class InstrMapping {
// Used to reduce search space only to the instructions using this
@@ -69,7 +69,7 @@ non-predicated form by assigning appropr
fields. For this relationship, non-predicated instructions are treated as key
instruction since they are the one used to query the interface function.
-.. code-block:: llvm
+.. code-block:: text
def getPredOpcode : InstrMapping {
// Choose a FilterClass that is used as a base class for all the
@@ -116,7 +116,7 @@ to include relevant information in its d
following to be the current definitions of ADD, ADD_pt (true) and ADD_pf (false)
instructions:
-.. code-block:: llvm
+.. code-block:: text
def ADD : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
"$dst = add($a, $b)",
@@ -137,7 +137,7 @@ In this step, we modify these instructio
required by the relationship model, <tt>getPredOpcode</tt>, so that they can
be related.
-.. code-block:: llvm
+.. code-block:: text
def ADD : PredRel, ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
"$dst = add($a, $b)",
Modified: vendor/llvm/dist/docs/InAlloca.rst
==============================================================================
--- vendor/llvm/dist/docs/InAlloca.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/InAlloca.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -41,7 +41,7 @@ that passes two default-constructed ``Fo
g(Foo(), Foo());
}
-.. code-block:: llvm
+.. code-block:: text
%struct.Foo = type { i32, i32 }
declare void @Foo_ctor(%struct.Foo* %this)
Modified: vendor/llvm/dist/docs/LangRef.rst
==============================================================================
--- vendor/llvm/dist/docs/LangRef.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/LangRef.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -839,7 +839,7 @@ Note that the Mach-O platform doesn't su
Here is an example of a COMDAT group where a function will only be selected if
the COMDAT key's section is the largest:
-.. code-block:: llvm
+.. code-block:: text
$foo = comdat largest
@foo = global i32 2, comdat($foo)
@@ -851,7 +851,7 @@ the COMDAT key's section is the largest:
As a syntactic sugar the ``$name`` can be omitted if the name is the same as
the global name:
-.. code-block:: llvm
+.. code-block:: text
$foo = comdat any
@foo = global i32 2, comdat
@@ -875,7 +875,7 @@ if a collision occurs in the symbol tabl
The combined use of COMDATS and section attributes may yield surprising results.
For example:
-.. code-block:: llvm
+.. code-block:: text
$foo = comdat any
$bar = comdat any
@@ -1205,7 +1205,7 @@ makes the format of the prologue data hi
A trivial example of valid prologue data for the x86 architecture is ``i8 144``,
which encodes the ``nop`` instruction:
-.. code-block:: llvm
+.. code-block:: text
define void @f() prologue i8 144 { ... }
@@ -1213,7 +1213,7 @@ Generally prologue data can be formed by
which skips the metadata, as in this example of valid prologue data for the
x86_64 architecture, where the first two bytes encode ``jmp .+10``:
-.. code-block:: llvm
+.. code-block:: text
%0 = type <{ i8, i8, i8* }>
@@ -2237,7 +2237,7 @@ source file name to the local function n
The syntax for the source file name is simply:
-.. code-block:: llvm
+.. code-block:: text
source_filename = "/path/to/source.c"
@@ -2847,7 +2847,7 @@ cleared low bit. However, in the ``%C``
allowed to assume that the '``undef``' operand could be the same as
``%Y``, allowing the whole '``select``' to be eliminated.
-.. code-block:: llvm
+.. code-block:: text
%A = xor undef, undef
@@ -2899,7 +2899,7 @@ does not execute at all. This allows us
code after it. Because the undefined operation "can't happen", the
optimizer can assume that it occurs in dead code.
-.. code-block:: llvm
+.. code-block:: text
a: store undef -> %X
b: store %X -> undef
@@ -3884,7 +3884,7 @@ their operand. For example:
Metadata nodes that aren't uniqued use the ``distinct`` keyword. For example:
-.. code-block:: llvm
+.. code-block:: text
!0 = distinct !{!"test\00", i32 10}
@@ -3949,7 +3949,7 @@ fields are tuples containing the debug i
unit, regardless of code optimizations (some nodes are only emitted if there are
references to them from instructions).
-.. code-block:: llvm
+.. code-block:: text
!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang",
isOptimized: true, flags: "-O2", runtimeVersion: 2,
@@ -3985,7 +3985,7 @@ DIBasicType
``DIBasicType`` nodes represent primitive types, such as ``int``, ``bool`` and
``float``. ``tag:`` defaults to ``DW_TAG_base_type``.
-.. code-block:: llvm
+.. code-block:: text
!0 = !DIBasicType(name: "unsigned char", size: 8, align: 8,
encoding: DW_ATE_unsigned_char)
@@ -3994,7 +3994,7 @@ DIBasicType
The ``encoding:`` describes the details of the type. Usually it's one of the
following:
-.. code-block:: llvm
+.. code-block:: text
DW_ATE_address = 1
DW_ATE_boolean = 2
@@ -4014,7 +4014,7 @@ refers to a tuple; the first operand is
types of the formal arguments in order. If the first operand is ``null``, that
represents a function with no return value (such as ``void foo() {}`` in C++).
-.. code-block:: llvm
+.. code-block:: text
!0 = !BasicType(name: "int", size: 32, align: 32, DW_ATE_signed)
!1 = !BasicType(name: "char", size: 8, align: 8, DW_ATE_signed_char)
@@ -4028,7 +4028,7 @@ DIDerivedType
``DIDerivedType`` nodes represent types derived from other types, such as
qualified types.
-.. code-block:: llvm
+.. code-block:: text
!0 = !DIBasicType(name: "unsigned char", size: 8, align: 8,
encoding: DW_ATE_unsigned_char)
@@ -4037,7 +4037,7 @@ qualified types.
The following ``tag:`` values are valid:
-.. code-block:: llvm
+.. code-block:: text
DW_TAG_member = 13
DW_TAG_pointer_type = 15
@@ -4089,7 +4089,7 @@ does not have ``flags: DIFlagFwdDecl``
together will unique such definitions at parse time via the ``identifier:``
field, even if the nodes are ``distinct``.
-.. code-block:: llvm
+.. code-block:: text
!0 = !DIEnumerator(name: "SixKind", value: 7)
!1 = !DIEnumerator(name: "SevenKind", value: 7)
@@ -4100,7 +4100,7 @@ field, even if the nodes are ``distinct`
The following ``tag:`` values are valid:
-.. code-block:: llvm
+.. code-block:: text
DW_TAG_array_type = 1
DW_TAG_class_type = 2
@@ -4219,7 +4219,7 @@ type with an ODR ``identifier:`` and tha
then the subprogram declaration is uniqued based only on its ``linkageName:``
and ``scope:``.
-.. code-block:: llvm
+.. code-block:: text
define void @_Z3foov() !dbg !0 {
...
@@ -4244,7 +4244,7 @@ DILexicalBlock
two lexical blocks at same depth. They are valid targets for ``scope:``
fields.
-.. code-block:: llvm
+.. code-block:: text
!0 = distinct !DILexicalBlock(scope: !1, file: !2, line: 7, column: 35)
@@ -4290,7 +4290,7 @@ the ``arg:`` field is set to non-zero, t
parameter, and it will be included in the ``variables:`` field of its
:ref:`DISubprogram`.
-.. code-block:: llvm
+.. code-block:: text
!0 = !DILocalVariable(name: "this", arg: 1, scope: !3, file: !2, line: 7,
type: !3, flags: DIFlagArtificial)
@@ -4313,7 +4313,7 @@ The current supported vocabulary is limi
- ``DW_OP_bit_piece, 16, 8`` specifies the offset and size (``16`` and ``8``
here, respectively) of the variable piece from the working expression.
-.. code-block:: llvm
+.. code-block:: text
!0 = !DIExpression(DW_OP_deref)
!1 = !DIExpression(DW_OP_plus, 3)
@@ -4336,7 +4336,7 @@ DIImportedEntity
``DIImportedEntity`` nodes represent entities (such as modules) imported into a
compile unit.
-.. code-block:: llvm
+.. code-block:: text
!2 = !DIImportedEntity(tag: DW_TAG_imported_module, name: "foo", scope: !0,
entity: !1, line: 7)
@@ -4349,7 +4349,7 @@ The ``name:`` field is the macro identif
defining a function-like macro, and the ``value`` field is the token-string
used to expand the macro identifier.
-.. code-block:: llvm
+.. code-block:: text
!2 = !DIMacro(macinfo: DW_MACINFO_define, line: 7, name: "foo(x)",
value: "((x) + 1)")
@@ -4362,7 +4362,7 @@ DIMacroFile
The ``nodes:`` field is a list of ``DIMacro`` and ``DIMacroFile`` nodes that
appear in the included source file.
-.. code-block:: llvm
+.. code-block:: text
!2 = !DIMacroFile(macinfo: DW_MACINFO_start_file, line: 7, file: !2,
nodes: !3)
@@ -5660,7 +5660,7 @@ block. Therefore, it must be the only no
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
dispatch1:
%cs1 = catchswitch within none [label %handler0, label %handler1] unwind to caller
@@ -5711,7 +5711,7 @@ the ``catchret``'s behavior is undefined
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
catchret from %catch label %continue
@@ -5761,7 +5761,7 @@ It transfers control to ``continue`` or
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
cleanupret from %cleanup unwind to caller
cleanupret from %cleanup unwind label %continue
@@ -5851,7 +5851,7 @@ unsigned and/or signed overflow, respect
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = add i32 4, %var ; yields i32:result = 4 + %var
@@ -5890,7 +5890,7 @@ optimizations:
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = fadd float 4.0, %var ; yields float:result = 4.0 + %var
@@ -5942,7 +5942,7 @@ unsigned and/or signed overflow, respect
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = sub i32 4, %var ; yields i32:result = 4 - %var
<result> = sub i32 0, %val ; yields i32:result = -%var
@@ -5985,7 +5985,7 @@ unsafe floating point optimizations:
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = fsub float 4.0, %var ; yields float:result = 4.0 - %var
<result> = fsub float -0.0, %val ; yields float:result = -%var
@@ -6039,7 +6039,7 @@ unsigned and/or signed overflow, respect
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = mul i32 4, %var ; yields i32:result = 4 * %var
@@ -6078,7 +6078,7 @@ unsafe floating point optimizations:
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = fmul float 4.0, %var ; yields float:result = 4.0 * %var
@@ -6122,7 +6122,7 @@ such, "((a udiv exact b) mul b) == a").
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = udiv i32 4, %var ; yields i32:result = 4 / %var
@@ -6168,7 +6168,7 @@ a :ref:`poison value <poisonvalues>` if
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = sdiv i32 4, %var ; yields i32:result = 4 / %var
@@ -6207,7 +6207,7 @@ unsafe floating point optimizations:
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = fdiv float 4.0, %var ; yields float:result = 4.0 / %var
@@ -6249,7 +6249,7 @@ Taking the remainder of a division by ze
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = urem i32 4, %var ; yields i32:result = 4 % %var
@@ -6304,7 +6304,7 @@ result of the division and the remainder
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = srem i32 4, %var ; yields i32:result = 4 % %var
@@ -6344,7 +6344,7 @@ to enable otherwise unsafe floating poin
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = frem float 4.0, %var ; yields float:result = 4.0 % %var
@@ -6406,7 +6406,7 @@ nsw/nuw bits in (mul %op1, (shl 1, %op2)
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = shl i32 4, %var ; yields i32: 4 << %var
<result> = shl i32 4, 2 ; yields i32: 16
@@ -6455,7 +6455,7 @@ non-zero.
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = lshr i32 4, 1 ; yields i32:result = 2
<result> = lshr i32 4, 2 ; yields i32:result = 1
@@ -6506,7 +6506,7 @@ non-zero.
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = ashr i32 4, 1 ; yields i32:result = 2
<result> = ashr i32 4, 2 ; yields i32:result = 1
@@ -6558,7 +6558,7 @@ The truth table used for the '``and``' i
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = and i32 4, %var ; yields i32:result = 4 & %var
<result> = and i32 15, 40 ; yields i32:result = 8
@@ -6657,7 +6657,7 @@ The truth table used for the '``xor``' i
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = xor i32 4, %var ; yields i32:result = 4 ^ %var
<result> = xor i32 15, 40 ; yields i32:result = 39
@@ -6710,7 +6710,7 @@ exceeds the length of ``val``, the resul
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = extractelement <4 x i32> %vec, i32 0 ; yields i32
@@ -6752,7 +6752,7 @@ undefined.
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = insertelement <4 x i32> %vec, i32 1, i32 0 ; yields <4 x i32>
@@ -6800,7 +6800,7 @@ only one vector.
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = shufflevector <4 x i32> %v1, <4 x i32> %v2,
<4 x i32> <i32 0, i32 4, i32 1, i32 5> ; yields <4 x i32>
@@ -6859,7 +6859,7 @@ the index operands.
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = extractvalue {i32, float} %agg, 0 ; yields i32
@@ -8126,7 +8126,7 @@ or :ref:`ptrtoint <i_ptrtoint>` instruct
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
%X = bitcast i8 255 to i8 ; yields i8 :-1
%Y = bitcast i32* %x to sint* ; yields sint*:%x
@@ -8265,7 +8265,7 @@ as the values being compared. Otherwise,
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = icmp eq i32 4, 5 ; yields: result=false
<result> = icmp ne float* %X, %X ; yields: result=false
@@ -8379,7 +8379,7 @@ assumptions to be made about the values
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
<result> = fcmp oeq float 4.0, 5.0 ; yields: result=false
<result> = fcmp one float 4.0, 5.0 ; yields: result=true
@@ -8815,7 +8815,7 @@ that does not carry an appropriate :ref:
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
dispatch:
%cs = catchswitch within none [label %handler0] unwind to caller
@@ -8885,7 +8885,7 @@ that does not carry an appropriate :ref:
Example:
""""""""
-.. code-block:: llvm
+.. code-block:: text
%tok = cleanuppad within %cs []
@@ -12481,19 +12481,19 @@ optimistic assumptions made during compi
``@llvm.experimental.deoptimize`` -- its body is defined to be
equivalent to:
-.. code-block:: llvm
+.. code-block:: text
- define void @llvm.experimental.guard(i1 %pred, <args...>) {
- %realPred = and i1 %pred, undef
- br i1 %realPred, label %continue, label %leave [, !make.implicit !{}]
-
- leave:
- call void @llvm.experimental.deoptimize(<args...>) [ "deopt"() ]
- ret void
-
- continue:
- ret void
- }
+ define void @llvm.experimental.guard(i1 %pred, <args...>) {
+ %realPred = and i1 %pred, undef
+ br i1 %realPred, label %continue, label %leave [, !make.implicit !{}]
+
+ leave:
+ call void @llvm.experimental.deoptimize(<args...>) [ "deopt"() ]
+ ret void
+
+ continue:
+ ret void
+ }
with the optional ``[, !make.implicit !{}]`` present if and only if it
Modified: vendor/llvm/dist/docs/MIRLangRef.rst
==============================================================================
--- vendor/llvm/dist/docs/MIRLangRef.rst Wed Aug 17 17:59:09 2016 (r304297)
+++ vendor/llvm/dist/docs/MIRLangRef.rst Wed Aug 17 19:33:52 2016 (r304298)
@@ -111,7 +111,6 @@ Here is an example of a YAML document th
.. code-block:: llvm
- --- |
define i32 @inc(i32* %x) {
entry:
%0 = load i32, i32* %x
@@ -119,7 +118,6 @@ Here is an example of a YAML document th
store i32 %1, i32* %x
ret i32 %1
}
- ...
.. _YAML block literal string: http://www.yaml.org/spec/1.2/spec.html#id2795688
@@ -129,7 +127,7 @@ Machine Functions
The remaining YAML documents contain the machine functions. This is an example
of such YAML document:
-.. code-block:: llvm
+.. code-block:: text
---
name: inc
@@ -172,7 +170,7 @@ A machine basic block is defined in a si
that contains the block's ID.
The example below defines two blocks that have an ID of zero and one:
-.. code-block:: llvm
+.. code-block:: text
bb.0:
<instructions>
@@ -182,7 +180,7 @@ The example below defines two blocks tha
A machine basic block can also have a name. It should be specified after the ID
in the block's definition:
-.. code-block:: llvm
+.. code-block:: text
bb.0.entry: ; This block's name is "entry"
<instructions>
@@ -196,7 +194,7 @@ Block References
The machine basic blocks are identified by their ID numbers. Individual
blocks are referenced using the following syntax:
-.. code-block:: llvm
+.. code-block:: text
%bb.<id>[.<name>]
@@ -213,7 +211,7 @@ Successors
The machine basic block's successors have to be specified before any of the
instructions:
-.. code-block:: llvm
+.. code-block:: text
bb.0.entry:
successors: %bb.1.then, %bb.2.else
@@ -227,7 +225,7 @@ The branch weights can be specified in b
The example below defines a block that has two successors with branch weights
of 32 and 16:
-.. code-block:: llvm
+.. code-block:: text
bb.0.entry:
successors: %bb.1.then(32), %bb.2.else(16)
@@ -240,7 +238,7 @@ Live In Registers
The machine basic block's live in registers have to be specified before any of
the instructions:
-.. code-block:: llvm
+.. code-block:: text
bb.0.entry:
liveins: %edi, %esi
@@ -255,7 +253,7 @@ Miscellaneous Attributes
The attributes ``IsAddressTaken``, ``IsLandingPad`` and ``Alignment`` can be
specified in brackets after the block's definition:
-.. code-block:: llvm
+.. code-block:: text
bb.0.entry (address-taken):
<instructions>
@@ -278,7 +276,7 @@ The instruction's name is usually specif
below shows an instance of the X86 ``RETQ`` instruction with a single machine
operand:
-.. code-block:: llvm
+.. code-block:: text
RETQ %eax
@@ -287,7 +285,7 @@ operands, the instruction's name has to
below shows an instance of the AArch64 ``LDPXpost`` instruction with three
defined register operands:
-.. code-block:: llvm
+.. code-block:: text
%sp, %fp, %lr = LDPXpost %sp, 2
@@ -303,7 +301,7 @@ Instruction Flags
The flag ``frame-setup`` can be specified before the instruction's name:
-.. code-block:: llvm
+.. code-block:: text
%fp = frame-setup ADDXri %sp, 0, 0
@@ -321,13 +319,13 @@ but they can also be used in a number of
The physical registers are identified by their name. They use the following
syntax:
-.. code-block:: llvm
+.. code-block:: text
%<name>
The example below shows three X86 physical registers:
-.. code-block:: llvm
+.. code-block:: text
%eax
%r15
@@ -336,13 +334,13 @@ The example below shows three X86 physic
The virtual registers are identified by their ID number. They use the following
syntax:
-.. code-block:: llvm
+.. code-block:: text
%<id>
Example:
-.. code-block:: llvm
+.. code-block:: text
%0
@@ -366,7 +364,7 @@ The immediate machine operands are untyp
example below shows an instance of the X86 ``MOV32ri`` instruction that has an
immediate machine operand ``-42``:
-.. code-block:: llvm
+.. code-block:: text
%eax = MOV32ri -42
@@ -384,14 +382,14 @@ machine operands. The register operands
and a reference to the tied register operand.
The full syntax of a register operand is shown below:
-.. code-block:: llvm
+.. code-block:: text
[<flags>] <register> [ :<subregister-idx-name> ] [ (tied-def <tied-op>) ]
This example shows an instance of the X86 ``XOR32rr`` instruction that has
5 register operands with different register flags:
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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