svn commit: r291492 - in head/sys/arm: arm include

Adrian Chadd adrian.chadd at gmail.com
Mon Nov 30 18:06:13 UTC 2015


Hiya!

What's the semantics of this?

The mips24k/mips74k cores support a kind of write combining but only
within a cache line - ie, it buffers writes to the same cache line,
then the first non-cacheline access flushes it out. It's for things
like accelerated framebuffer writes. Is this similar to what you've
just added?


-a


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