svn commit: r290647 - head/sys/arm/arm

Michal Meloun mmel at FreeBSD.org
Tue Nov 10 11:45:43 UTC 2015


Author: mmel
Date: Tue Nov 10 11:45:41 2015
New Revision: 290647
URL: https://svnweb.freebsd.org/changeset/base/290647

Log:
  ARM: Improve robustness of locore_v6.S and fix errors.
  - boot page table is not allocated in data section, so must be
    cleared before use
  - map only one section (1 MB) for SOCDEV mapping (*)
  - DSB must be used for ensuring of finishing TLB operations
  - Invalidate BTB when appropriate
  
  PR:		198360
  Reported by:	Daisuke Aoyama <aoyama at peach.ne.jp> (*)
  Approved by:	kib (mentor)

Modified:
  head/sys/arm/arm/locore-v6.S

Modified: head/sys/arm/arm/locore-v6.S
==============================================================================
--- head/sys/arm/arm/locore-v6.S	Tue Nov 10 11:28:02 2015	(r290646)
+++ head/sys/arm/arm/locore-v6.S	Tue Nov 10 11:45:41 2015	(r290647)
@@ -142,9 +142,11 @@ ASENTRY_NP(_start)
 	orr	r7, #CPU_CONTROL_AFLT_ENABLE
 	orr	r7, #CPU_CONTROL_VECRELOC
 	mcr	CP15_SCTLR(r7)
+	DSB
 	ISB
 	bl	dcache_inv_poc_all
 	mcr	CP15_ICIALLU
+	DSB
 	ISB
 
 	/*
@@ -155,6 +157,14 @@ ASENTRY_NP(_start)
 	adr	r0, Lpagetable
 	bl	translate_va_to_pa
 
+	/* Clear boot page table */
+	mov	r1, r0
+	mov	r2, L1_TABLE_SIZE
+	mov	r3,#0
+1:	str	r3, [r1], #4
+	subs	r2, #4
+	bgt	1b
+
 	/*
 	 * Map PA == VA
 	 */
@@ -174,9 +184,10 @@ ASENTRY_NP(_start)
 	bl	build_pagetables
 
 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
-	/* Create the custom map used for early_printf(). */
+	/* Create the custom map (1MB) used for early_printf(). */
 	ldr	r1, =SOCDEV_PA
 	ldr	r2, =SOCDEV_VA
+	mov	r3, #1
 	bl	build_pagetables
 #endif
 	bl	init_mmu
@@ -300,7 +311,9 @@ ASENTRY_NP(init_mmu)
 	ISB
 	mcr	CP15_TLBIALL		/* Flush TLB */
 	mcr	CP15_BPIALL		/* Flush Branch predictor */
+	DSB
 	ISB
+
 	mov	pc, lr
 END(init_mmu)
 
@@ -328,6 +341,7 @@ ASENTRY_NP(reinit_mmu)
 	bl	dcache_inv_pou_all
 #endif
 	mcr	CP15_ICIALLU
+	DSB
 	ISB
 
 	/* Set auxiliary register */
@@ -336,6 +350,7 @@ ASENTRY_NP(reinit_mmu)
 	eor 	r8, r8, r6		/* Set bits */
 	teq 	r7, r8
 	mcrne 	CP15_ACTLR(r8)
+	DSB
 	ISB
 
 	/* Enable caches. */
@@ -350,8 +365,8 @@ ASENTRY_NP(reinit_mmu)
 	DSB
 	ISB
 
-	/* Flush all TLBs */
-	mcr	CP15_TLBIALL
+	mcr	CP15_TLBIALL		/* Flush TLB */
+	mcr	CP15_BPIALL		/* Flush Branch predictor */
 	DSB
 	ISB
 
@@ -362,6 +377,7 @@ ASENTRY_NP(reinit_mmu)
 	bl	dcache_inv_pou_all
 #endif
 	mcr	CP15_ICIALLU
+	DSB
 	ISB
 
 	pop	{r4-r11, pc}
@@ -453,11 +469,13 @@ ASENTRY_NP(mpentry)
 	orr	r0, #CPU_CONTROL_AFLT_ENABLE
 	orr	r0, #CPU_CONTROL_VECRELOC
 	mcr	CP15_SCTLR(r0)
+	DSB
 	ISB
 
 	/* Invalidate L1 cache I+D cache */
 	bl	dcache_inv_pou_all
 	mcr	CP15_ICIALLU
+	DSB
 	ISB
 
 	/* Find the delta between VA and PA */


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