svn commit: r279699 - in head/sys: amd64/amd64 i386/i386

[Slawa Olhovchenkov]

On Mon, Mar 09, 2015 at 07:42:52PM +0200, Konstantin Belousov wrote:

> On Fri, Mar 06, 2015 at 08:34:28PM +0000, John Baldwin wrote:
> > Author: jhb
> > Date: Fri Mar  6 20:34:28 2015
> > New Revision: 279699
> > URL: https://svnweb.freebsd.org/changeset/base/279699
> > 
> > Log:
> >   Only schedule interrupts on a single hyperthread of a modern Intel CPU core
> >   by default.  Previously we used a single hyperthread on Pentium4-era
> >   cores but used both hyperthreads on more recent CPUs.
> >   
> >   MFC after:	2 weeks
> > 
> > Modified:
> >   head/sys/amd64/amd64/mp_machdep.c
> >   head/sys/i386/i386/mp_machdep.c
> > 
> > Modified: head/sys/amd64/amd64/mp_machdep.c
> > ==============================================================================
> > --- head/sys/amd64/amd64/mp_machdep.c	Fri Mar  6 16:43:54 2015	(r279698)
> > +++ head/sys/amd64/amd64/mp_machdep.c	Fri Mar  6 20:34:28 2015	(r279699)
> > @@ -828,8 +828,8 @@ set_interrupt_apic_ids(void)
> >  			continue;
> >  
> >  		/* Don't let hyperthreads service interrupts. */
> > -		if (hyperthreading_cpus > 1 &&
> > -		    apic_id % hyperthreading_cpus != 0)
> > +		if (cpu_logical > 1 &&
> > +		    apic_id % cpu_logical != 0)
> >  			continue;
> >  
> >  		intr_add_cpu(i);
> > 
> > Modified: head/sys/i386/i386/mp_machdep.c
> > ==============================================================================
> > --- head/sys/i386/i386/mp_machdep.c	Fri Mar  6 16:43:54 2015	(r279698)
> > +++ head/sys/i386/i386/mp_machdep.c	Fri Mar  6 20:34:28 2015	(r279699)
> > @@ -842,8 +842,8 @@ set_interrupt_apic_ids(void)
> >  			continue;
> >  
> >  		/* Don't let hyperthreads service interrupts. */
> > -		if (hyperthreading_cpus > 1 &&
> > -		    apic_id % hyperthreading_cpus != 0)
> > +		if (cpu_logical > 1 &&
> > +		    apic_id % cpu_logical != 0)
> >  			continue;
> >  
> >  		intr_add_cpu(i);
> 
> BTW, this sounds somewhat backward from the intention of the HTT/SMT.
> The feature was aimed to reduce latency of memory or device registers
> reads by allowing several contexts to stuck on the cache line fill
> or waiting for the device response to read request.
> 
> Since typical interrupt handler just EOIs the source or does nothing at
> all to the source, what is the reasoning behind the change ?

typical interrupt handler do TCP work?