svn commit: r279514 - head/sys/mips/conf
Adrian Chadd
adrian at FreeBSD.org
Mon Mar 2 02:27:27 UTC 2015
Author: adrian
Date: Mon Mar 2 02:27:25 2015
New Revision: 279514
URL: https://svnweb.freebsd.org/changeset/base/279514
Log:
Add support for the AP135 2.0 reference platform.
This is a QCA9558 SoC (2ghz 3x3) with an atheros 11ac PCIe 5GHz 3x3
NIC and an AR8327 gigabit ethernet switch.
TODO:
* The AR8327 gigabit switch support bugfixes are forthcoming.
* 11ac support and 11ac NIC support
Added:
head/sys/mips/conf/AP135 (contents, props changed)
head/sys/mips/conf/AP135.hints (contents, props changed)
Added: head/sys/mips/conf/AP135
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/mips/conf/AP135 Mon Mar 2 02:27:25 2015 (r279514)
@@ -0,0 +1,60 @@
+#
+# AP135 - the QCA955x SoC reference design
+#
+# This contains a QCA9558 MIPS74k SoC with on-board 3x3 2GHz wifi,
+# 128MiB RAM, an AR8327 5-port gigabit ethernet switch and
+# a QCA 11ac 5GHz AP NIC.
+#
+# The to things not currently support are the QCA 11ac NIC and
+# PCIe host controllers - there's two of them, and the existing
+# PCIe code here doesn't support that just yet.
+#
+# $FreeBSD$
+#
+
+# Include the default QCA955x parameters
+include "QCA955X_BASE"
+
+ident AP135
+
+# Override hints with board values
+hints "AP135.hints"
+
+# Force the board memory - the base AP135 has 128MB RAM
+options AR71XX_REALMEM=(128*1024*1024)
+
+# i2c GPIO bus
+#device gpioiic
+#device iicbb
+#device iicbus
+#device iic
+
+# Options required for miiproxy and mdiobus
+options ARGE_MDIO # Export an MDIO bus separate from arge
+device miiproxy # MDIO bus <-> MII PHY rendezvous
+
+device etherswitch
+device arswitch
+
+# read MSDOS formatted disks - USB
+#options MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options AR71XX_ENV_UBOOT
+
+# uzip - to boot natively from flash
+device geom_uncompress
+options GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device geom_map
+
+# yes, this board has a PCI connected atheros device
+device ath_pci
+options AR71XX_ATH_EEPROM
+device firmware # Used by the above
+options ATH_EEPROM_FIRMWARE
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
Added: head/sys/mips/conf/AP135.hints
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/mips/conf/AP135.hints Mon Mar 2 02:27:25 2015 (r279514)
@@ -0,0 +1,166 @@
+# This is a placeholder until the hardware support is complete.
+
+# I'm assuming this is an AP135-020. The AP136-010 in openwrt has
+# the ethernet ports wired up to the switch in the reverse way.
+
+# $FreeBSD$
+
+# QCA955X_ETH_CFG_RGMII_EN (1 << 0)
+hint.qca955x_gmac.0.gmac_cfg=0x1
+
+# mdiobus0 on arge0
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# AR8327 - connected via mdiobus0 on arge0
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=0 # definitely not the internal switch!
+hint.arswitch.0.is_9340=0 # not the internal switch!
+hint.arswitch.0.numphys=5 # all ports are PHYs
+hint.arswitch.0.phy4cpu=0
+hint.arswitch.0.is_rgmii=0 # not needed
+hint.arswitch.0.is_gmii=0 # not needed
+
+# This is where it gets a bit odd. port 0 and port 6 are CPU ports.
+# The current code only supports one CPU port. So hm, what should
+# we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
+
+# The other trick - how do we get arge1 (hooked up to GMAC0) to work?
+# That's currently supposed to be hooked up to CPU port 0.
+
+# Other AR8327 configuration parameters
+
+# AP136-020 parameters
+
+# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
+
+# AR8327_PAD_MAC_SGMII
+hint.arswitch.0.pad.0.mode=3
+#hint.arswitch.0.pad.0.rxclk_delay_sel=0
+hint.arswitch.0.pad.0.sgmii_delay_en=1
+
+# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
+
+# AR8327_PAD_MAC_RGMII
+# XXX I think this hooks it up to the internal MAC6
+hint.arswitch.0.pad.6.mode=6
+hint.arswitch.0.pad.6.txclk_delay_en=1
+hint.arswitch.0.pad.6.rxclk_delay_en=1
+# AR8327_CLK_DELAY_SEL1
+hint.arswitch.0.pad.6.txclk_delay_sel=1
+# AR8327_CLK_DELAY_SEL2
+hint.arswitch.0.pad.6.rxclk_delay_sel=2
+
+# XXX there's no LED management just yet!
+hint.arswitch.0.led.ctrl0=0x00000000
+hint.arswitch.0.led.ctrl1=0xc737c737
+hint.arswitch.0.led.ctrl2=0x00000000
+hint.arswitch.0.led.ctrl3=0x00c30c00
+hint.arswitch.0.led.open_drain=1
+
+# force_link=1 is required for the rest of the parameters
+# to be configured.
+hint.arswitch.0.port.0.force_link=1
+hint.arswitch.0.port.0.speed=1000
+hint.arswitch.0.port.0.duplex=1
+hint.arswitch.0.port.0.txpause=1
+hint.arswitch.0.port.0.rxpause=1
+
+# force_link=1 is required for the rest of the parameters
+# to be configured.
+hint.arswitch.0.port.6.force_link=1
+hint.arswitch.0.port.6.speed=1000
+hint.arswitch.0.port.6.duplex=1
+hint.arswitch.0.port.6.txpause=1
+hint.arswitch.0.port.6.rxpause=1
+
+# arge0 - hooked up to AR8327 GMAC6, RGMII
+hint.arge.0.phymask=0x10
+hint.arge.0.miimode=3 # RGMII
+hint.arge.0.pll_1000=0x56000000
+
+# MAC for arge0 is the first 6 bytes of the ART
+hint.arge.0.eeprommac=0x1fff0000
+
+# arge1 - lock up to 1000/full
+hint.arge.1.phymask=0x0
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+hint.arge.1.miimode=5 # SGMII
+hint.arge.1.pll_1000=0x03000101
+
+# MAC for arge1 is the second 6 bytes of the ART
+hint.arge.1.eeprommac=0x1fff0006
+
+# ath0: Where the ART is - last 64k in the flash
+hint.ath.0.eepromaddr=0x1fff0000
+hint.ath.0.eepromsize=16384
+
+# ath1: it's different; it's a PCIe attached device, so
+# we instead need to teach the PCIe bridge code about it
+# (ie, the 'early pci fixup' stuff that programs the PCIe
+# host registers on the NIC) and then we teach ath where
+# to find it.
+
+# ath1 hint - pcie slot 0
+hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
+hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
+
+# ath0 - eeprom comes from here
+hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+
+# flash layout:
+#
+# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),8256k(mib0),64k(ART)
+
+
+# 256KiB u-boot
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000 # 256k u-boot
+hint.map.0.name="u-boot"
+hint.map.0.readonly=1
+
+# 64KiB u-boot-env
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000 # 64k u-boot-env
+hint.map.1.name="u-boot-env"
+hint.map.1.readonly=1
+
+# 6336KiB rootfs
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x00680000 # 6336k rootfs
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+# 1344KiB uImage
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x00680000
+hint.map.3.end=0x007d0000 # 1408k uImage, 64k off the end..
+hint.map.3.name="uImage"
+hint.map.3.readonly=1
+
+# 64KiB cfg
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x007d0000
+hint.map.4.end=0x007e0000
+hint.map.4.name="cfg"
+hint.map.4.readonly=0
+
+# 8256 KiB mib0
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x007e0000
+hint.map.5.end=0x00ff0000 # 64k mib0
+hint.map.5.name="mib0"
+hint.map.5.readonly=1
+
+# 64KiB ART
+hint.map.6.at="flash/spi0"
+hint.map.6.start=0x007f0000
+hint.map.6.end=0x01000000 # 64k ART
+hint.map.6.name="ART"
+hint.map.6.readonly=1
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