svn commit: r284267 - stable/10/sys/dev/mrsas
Kashyap D Desai
kadesai at FreeBSD.org
Thu Jun 11 14:11:43 UTC 2015
Author: kadesai
Date: Thu Jun 11 14:11:41 2015
New Revision: 284267
URL: https://svnweb.freebsd.org/changeset/base/284267
Log:
MFC r282525-282533
r282533 : Corrected indentation on conflicted source files.
r282532 : Configured the mrsas(4) driver to support UNMAPPED I/O and updated driver version.
r282531 :
1. All LSI namings are converted to AVAGO Tech.
2. Fix in AEN path(suggested by John Baldwin).
3. Fix IOCTL path w.r.t Sense key handling
r282530 :
Bug fixes found internally as detailed below:
1. While disabling interrupt the FW disables interrupts for only 16 vectors.
In case of Invader which supports 96 MSI-x vectors, some spurious interrupts
may come on other vectors even after interrupt disable. So, driver uses a flag
and ignores the spurious interrupts.
2. Reply queue depth is made double the number of commands supported by FW.
3. Misplaced interrupt enable code is now moved down in the OCR path.
4. Updated error handling code in OCR path.
5. Removed un-necessary print.
r282529 :
Driver calls mrsas_complete_cmd() to call mrsas_wakeup() for each MFI frame that was
issued through the ioctl() interface prior to the kill adapter. This ensures
userspace ioctl() system calls issued just before a kill adapter don't get stuck in
wait state and IOCTLs are returned to application.
r282528 :
In OCR(Online Controller Reset) path, driver sets adapter state to
MEGASAS_HBA_OPERATIONAL before getting new RAID map.
There will be a small window where IO will come from OS with old RAID map.
This patch will update adapter state to MEGASAS_HBA_OPERATIONAL,
only after driver has new RAID map to avoid any IOs getting build using old RAID map.
r282527 :
Current driver does fast path read load balancing between arm and mirror disk
for two Drive Raid-1 configuration only.
Now, Driver support fast path read load balancing for all (any number of disk) Raid-1 configuration.
r282526 :
Now Driver expose Secure Jbod Support via driver_operations in MFI INIT Frame.
FW expose Secure Jbod support via Controller properity.
Firmware expect IOs to be received from different IO path than
conventional fast path queue, in case of SED drives.
To have Secure jbod support user need driver and firmware support.
r282525 : This patch adds the feature to provide PCI information via IOCTL query.
Modified:
stable/10/sys/dev/mrsas/mrsas.c
stable/10/sys/dev/mrsas/mrsas.h
stable/10/sys/dev/mrsas/mrsas_cam.c
stable/10/sys/dev/mrsas/mrsas_fp.c
stable/10/sys/dev/mrsas/mrsas_ioctl.c
stable/10/sys/dev/mrsas/mrsas_ioctl.h
stable/10/sys/dev/mrsas/mrsas_linux.c
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/sys/dev/mrsas/mrsas.c
==============================================================================
--- stable/10/sys/dev/mrsas/mrsas.c Thu Jun 11 14:02:23 2015 (r284266)
+++ stable/10/sys/dev/mrsas/mrsas.c Thu Jun 11 14:11:41 2015 (r284267)
@@ -1,6 +1,7 @@
/*
+ * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy
* Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
- * Support: freebsdraid at lsi.com
+ * Support: freebsdraid at avagotech.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -31,7 +32,7 @@
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
- * Send feedback to: <megaraidfbsd at lsi.com> Mail to: LSI Corporation, 1621
+ * Send feedback to: <megaraidfbsd at avagotech.com> Mail to: AVAGO TECHNOLOGIES 1621
* Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
*
*/
@@ -81,16 +82,19 @@ static int mrsas_init_fw(struct mrsas_so
static int mrsas_setup_raidmap(struct mrsas_softc *sc);
static int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex);
static int mrsas_clear_intr(struct mrsas_softc *sc);
-static int
-mrsas_get_ctrl_info(struct mrsas_softc *sc,
- struct mrsas_ctrl_info *ctrl_info);
-static int
+static int mrsas_get_ctrl_info(struct mrsas_softc *sc);
+static void mrsas_update_ext_vd_details(struct mrsas_softc *sc);
+static int
mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *cmd_to_abort);
+static struct mrsas_softc *
+mrsas_get_softc_instance(struct cdev *dev,
+ u_long cmd, caddr_t arg);
u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
-u_int8_t
+u_int8_t
mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *mfi_cmd);
+void mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc);
int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr);
int mrsas_init_adapter(struct mrsas_softc *sc);
int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc);
@@ -102,10 +106,10 @@ int mrsas_issue_dcmd(struct mrsas_softc
int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
int mrsas_reset_ctrl(struct mrsas_softc *sc);
int mrsas_wait_for_outstanding(struct mrsas_softc *sc);
-int
+int
mrsas_issue_blocked_cmd(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *cmd);
-int
+int
mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd,
int size);
void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd);
@@ -122,17 +126,17 @@ void mrsas_teardown_intr(struct mrsas_so
void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
void mrsas_kill_hba(struct mrsas_softc *sc);
void mrsas_aen_handler(struct mrsas_softc *sc);
-void
+void
mrsas_write_reg(struct mrsas_softc *sc, int offset,
u_int32_t value);
-void
+void
mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
u_int32_t req_desc_hi);
void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
-void
+void
mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *cmd, u_int8_t status);
-void
+void
mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status,
u_int8_t extStatus);
struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
@@ -175,9 +179,9 @@ typedef struct mrsas_ident {
} MRSAS_CTLR_ID;
MRSAS_CTLR_ID device_table[] = {
- {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "LSI Thunderbolt SAS Controller"},
- {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "LSI Invader SAS Controller"},
- {0x1000, MRSAS_FURY, 0xffff, 0xffff, "LSI Fury SAS Controller"},
+ {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "AVAGO Thunderbolt SAS Controller"},
+ {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "AVAGO Invader SAS Controller"},
+ {0x1000, MRSAS_FURY, 0xffff, 0xffff, "AVAGO Fury SAS Controller"},
{0, 0, 0, 0, NULL}
};
@@ -272,6 +276,7 @@ mrsas_disable_intr(struct mrsas_softc *s
u_int32_t mask = 0xFFFFFFFF;
u_int32_t status;
+ sc->mask_interrupts = 1;
mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask);
/* Dummy read to force pci flush */
status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
@@ -283,6 +288,7 @@ mrsas_enable_intr(struct mrsas_softc *sc
u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK;
u_int32_t status;
+ sc->mask_interrupts = 0;
mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0);
status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status));
@@ -352,7 +358,7 @@ mrsas_probe(device_t dev)
if ((id = mrsas_find_ident(dev)) != NULL) {
if (first_ctrl) {
- printf("LSI MegaRAID SAS FreeBSD mrsas driver version: %s\n",
+ printf("AVAGO MegaRAID SAS FreeBSD mrsas driver version: %s\n",
MRSAS_VERSION);
first_ctrl = 0;
}
@@ -460,6 +466,11 @@ mrsas_get_tunables(struct mrsas_softc *s
*/
TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug);
+ /*
+ * Grab the global variables.
+ */
+ TUNABLE_INT_FETCH("hw.mrsas.lb_pending_cmds", &sc->lb_pending_cmds);
+
/* Grab the unit-instance variables */
snprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level",
device_get_unit(sc->mrsas_dev));
@@ -1163,6 +1174,12 @@ mrsas_free_mem(struct mrsas_softc *sc)
*/
if (sc->mrsas_parent_tag != NULL)
bus_dma_tag_destroy(sc->mrsas_parent_tag);
+
+ /*
+ * Free ctrl_info memory
+ */
+ if (sc->ctrl_info != NULL)
+ free(sc->ctrl_info, M_MRSAS);
}
/*
@@ -1231,6 +1248,43 @@ mrsas_resume(device_t dev)
return (0);
}
+/**
+ * mrsas_get_softc_instance: Find softc instance based on cmd type
+ *
+ * This function will return softc instance based on cmd type.
+ * In some case, application fire ioctl on required management instance and
+ * do not provide host_no. Use cdev->si_drv1 to get softc instance for those
+ * case, else get the softc instance from host_no provided by application in
+ * user data.
+ */
+
+static struct mrsas_softc *
+mrsas_get_softc_instance(struct cdev *dev, u_long cmd, caddr_t arg)
+{
+ struct mrsas_softc *sc = NULL;
+ struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
+
+ if (cmd == MRSAS_IOC_GET_PCI_INFO) {
+ sc = dev->si_drv1;
+ } else {
+ /*
+ * get the Host number & the softc from data sent by the
+ * Application
+ */
+ sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
+ if ((user_ioc->host_no >= mrsas_mgmt_info.max_index) || (sc == NULL)) {
+ if (sc == NULL)
+ mrsas_dprint(sc, MRSAS_FAULT,
+ "There is no Controller number %d .\n", user_ioc->host_no);
+ else
+ mrsas_dprint(sc, MRSAS_FAULT,
+ "Invalid Controller number %d .\n", user_ioc->host_no);
+ }
+ }
+
+ return sc;
+}
+
/*
* mrsas_ioctl: IOCtl commands entry point.
*
@@ -1242,19 +1296,12 @@ mrsas_ioctl(struct cdev *dev, u_long cmd
{
struct mrsas_softc *sc;
int ret = 0, i = 0;
+ MRSAS_DRV_PCI_INFORMATION *pciDrvInfo;
- struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
-
- /* get the Host number & the softc from data sent by the Application */
- sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
-
- if ((mrsas_mgmt_info.max_index == user_ioc->host_no) || (sc == NULL)) {
- printf("Please check the controller number\n");
- if (sc == NULL)
- printf("There is NO such Host no. %d\n", user_ioc->host_no);
-
+ sc = mrsas_get_softc_instance(dev, cmd, arg);
+ if (!sc)
return ENOENT;
- }
+
if (sc->remove_in_progress) {
mrsas_dprint(sc, MRSAS_INFO,
"Driver remove or shutdown called.\n");
@@ -1298,6 +1345,22 @@ do_ioctl:
case MRSAS_IOC_SCAN_BUS:
ret = mrsas_bus_scan(sc);
break;
+
+ case MRSAS_IOC_GET_PCI_INFO:
+ pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *) arg;
+ memset(pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION));
+ pciDrvInfo->busNumber = pci_get_bus(sc->mrsas_dev);
+ pciDrvInfo->deviceNumber = pci_get_slot(sc->mrsas_dev);
+ pciDrvInfo->functionNumber = pci_get_function(sc->mrsas_dev);
+ pciDrvInfo->domainID = pci_get_domain(sc->mrsas_dev);
+ mrsas_dprint(sc, MRSAS_INFO, "pci bus no: %d,"
+ "pci device no: %d, pci function no: %d,"
+ "pci domain ID: %d\n",
+ pciDrvInfo->busNumber, pciDrvInfo->deviceNumber,
+ pciDrvInfo->functionNumber, pciDrvInfo->domainID);
+ ret = 0;
+ break;
+
default:
mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd);
ret = ENOENT;
@@ -1327,8 +1390,10 @@ mrsas_poll(struct cdev *dev, int poll_ev
}
if (revents == 0) {
if (poll_events & (POLLIN | POLLRDNORM)) {
+ mtx_lock(&sc->aen_lock);
sc->mrsas_poll_waiting = 1;
selrecord(td, &sc->mrsas_select);
+ mtx_unlock(&sc->aen_lock);
}
}
return revents;
@@ -1386,6 +1451,9 @@ mrsas_isr(void *arg)
struct mrsas_softc *sc = irq_context->sc;
int status = 0;
+ if (sc->mask_interrupts)
+ return;
+
if (!sc->msix_vectors) {
status = mrsas_clear_intr(sc);
if (!status)
@@ -1423,7 +1491,7 @@ mrsas_complete_cmd(struct mrsas_softc *s
MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req;
struct mrsas_mpt_cmd *cmd_mpt;
struct mrsas_mfi_cmd *cmd_mfi;
- u_int8_t arm, reply_descript_type;
+ u_int8_t reply_descript_type;
u_int16_t smid, num_completed;
u_int8_t status, extStatus;
union desc_value desc_val;
@@ -1461,8 +1529,7 @@ mrsas_complete_cmd(struct mrsas_softc *s
device_id = cmd_mpt->ccb_ptr->ccb_h.target_id;
lbinfo = &sc->load_balance_info[device_id];
if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) {
- arm = lbinfo->raid1DevHandle[0] == scsi_io_req->DevHandle ? 0 : 1;
- mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[arm]);
+ mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]);
cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG;
}
/* Fall thru and complete IO */
@@ -1607,8 +1674,8 @@ mrsas_map_mpt_cmd_status(struct mrsas_mp
static int
mrsas_alloc_mem(struct mrsas_softc *sc)
{
- u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size,
- evt_detail_size, count;
+ u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size,
+ chain_frame_size, evt_detail_size, count;
/*
* Allocate parent DMA tag
@@ -1860,34 +1927,6 @@ mrsas_setup_raidmap(struct mrsas_softc *
{
int i;
- sc->drv_supported_vd_count =
- MRSAS_MAX_LD_CHANNELS * MRSAS_MAX_DEV_PER_CHANNEL;
- sc->drv_supported_pd_count =
- MRSAS_MAX_PD_CHANNELS * MRSAS_MAX_DEV_PER_CHANNEL;
-
- if (sc->max256vdSupport) {
- sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
- sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
- } else {
- sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
- sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
- }
-
-#if VD_EXT_DEBUG
- device_printf(sc->mrsas_dev, "FW supports: max256vdSupport = %s\n",
- sc->max256vdSupport ? "YES" : "NO");
- device_printf(sc->mrsas_dev, "FW supports %dVDs %dPDs\n"
- "DRIVER supports %dVDs %dPDs \n",
- sc->fw_supported_vd_count, sc->fw_supported_pd_count,
- sc->drv_supported_vd_count, sc->drv_supported_pd_count);
-#endif
-
- sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
- (sizeof(MR_LD_SPAN_MAP) * (sc->fw_supported_vd_count - 1));
- sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
- sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) +
- (sizeof(MR_LD_SPAN_MAP) * (sc->drv_supported_vd_count - 1));
-
for (i = 0; i < 2; i++) {
sc->ld_drv_map[i] =
(void *)malloc(sc->drv_map_sz, M_MRSAS, M_NOWAIT);
@@ -1902,14 +1941,6 @@ mrsas_setup_raidmap(struct mrsas_softc *
}
}
- sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
-
- if (sc->max256vdSupport)
- sc->current_map_sz = sc->new_map_sz;
- else
- sc->current_map_sz = sc->old_map_sz;
-
-
for (int i = 0; i < 2; i++) {
if (bus_dma_tag_create(sc->mrsas_parent_tag,
4, 0,
@@ -1969,7 +2000,7 @@ ABORT:
* get_pdlist, get_ld_list and max_sectors are currently not being used, it
* is left here as placeholder.
*/
-static int
+static int
mrsas_init_fw(struct mrsas_softc *sc)
{
@@ -1977,7 +2008,6 @@ mrsas_init_fw(struct mrsas_softc *sc)
u_int32_t max_sectors_1;
u_int32_t max_sectors_2;
u_int32_t tmp_sectors;
- struct mrsas_ctrl_info *ctrl_info;
u_int32_t scratch_pad_2;
int msix_enable = 0;
int fw_msix_count = 0;
@@ -2039,23 +2069,25 @@ mrsas_init_fw(struct mrsas_softc *sc)
device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
return (1);
}
+ sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
+ if (!sc->ctrl_info) {
+ device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");
+ return (1);
+ }
/*
* Get the controller info from FW, so that the MAX VD support
* availability can be decided.
*/
- ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
- if (!ctrl_info)
- device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");
-
- if (mrsas_get_ctrl_info(sc, ctrl_info)) {
+ if (mrsas_get_ctrl_info(sc)) {
device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n");
+ return (1);
}
- sc->max256vdSupport =
- (u_int8_t)ctrl_info->adapterOperations3.supportMaxExtLDs;
+ sc->secure_jbod_support =
+ (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
+
+ if (sc->secure_jbod_support)
+ device_printf(sc->mrsas_dev, "FW supports SED \n");
- if (ctrl_info->max_lds > 64) {
- sc->max256vdSupport = 1;
- }
if (mrsas_setup_raidmap(sc) != SUCCESS) {
device_printf(sc->mrsas_dev, "Set up RAID map failed.\n");
return (1);
@@ -2079,9 +2111,9 @@ mrsas_init_fw(struct mrsas_softc *sc)
* calculate max_sectors_1. So the number ended up as zero always.
*/
tmp_sectors = 0;
- max_sectors_1 = (1 << ctrl_info->stripe_sz_ops.min) *
- ctrl_info->max_strips_per_io;
- max_sectors_2 = ctrl_info->max_request_size;
+ max_sectors_1 = (1 << sc->ctrl_info->stripe_sz_ops.min) *
+ sc->ctrl_info->max_strips_per_io;
+ max_sectors_2 = sc->ctrl_info->max_request_size;
tmp_sectors = min(max_sectors_1, max_sectors_2);
sc->max_sectors_per_req = sc->max_num_sge * MRSAS_PAGE_SIZE / 512;
@@ -2089,9 +2121,9 @@ mrsas_init_fw(struct mrsas_softc *sc)
sc->max_sectors_per_req = tmp_sectors;
sc->disableOnlineCtrlReset =
- ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
+ sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
sc->UnevenSpanSupport =
- ctrl_info->adapterOperations2.supportUnevenSpans;
+ sc->ctrl_info->adapterOperations2.supportUnevenSpans;
if (sc->UnevenSpanSupport) {
device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n",
sc->UnevenSpanSupport);
@@ -2101,9 +2133,6 @@ mrsas_init_fw(struct mrsas_softc *sc)
else
sc->fast_path_io = 0;
}
- if (ctrl_info)
- free(ctrl_info, M_MRSAS);
-
return (0);
}
@@ -2135,7 +2164,7 @@ mrsas_init_adapter(struct mrsas_softc *s
max_cmd = sc->max_fw_cmds;
/* Determine allocation size of command frames */
- sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16);
+ sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16) * 2;
sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd;
sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1));
@@ -2280,7 +2309,9 @@ mrsas_ioc_init(struct mrsas_softc *sc)
init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr;
init_frame->driver_ver_hi = 0;
}
+ init_frame->driver_operations.mfi_capabilities.support_ndrive_r1_lb = 1;
init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1;
+ init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1;
phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024;
init_frame->queue_info_new_phys_addr_lo = phys_addr;
init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t);
@@ -2422,7 +2453,7 @@ mrsas_alloc_mpt_cmds(struct mrsas_softc
* This functions fires the command to Firmware by writing to the
* inbound_low_queue_port and inbound_high_queue_port.
*/
-void
+void
mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
u_int32_t req_desc_hi)
{
@@ -2702,7 +2733,6 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
/* Reset not supported, kill adapter */
mrsas_dprint(sc, MRSAS_OCR, "Reset not supported, killing adapter.\n");
mrsas_kill_hba(sc);
- sc->adprecovery = MRSAS_HW_CRITICAL_ERROR;
retval = FAIL;
goto out;
}
@@ -2787,10 +2817,6 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n");
continue;
}
- mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
- mrsas_enable_intr(sc);
- sc->adprecovery = MRSAS_HBA_OPERATIONAL;
-
/* Re-fire management commands */
for (j = 0; j < sc->max_fw_cmds; j++) {
mpt_cmd = sc->mpt_cmd_list[j];
@@ -2820,9 +2846,18 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
memset(sc->load_balance_info, 0,
sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES_EXT);
+ if (mrsas_get_ctrl_info(sc)) {
+ mrsas_kill_hba(sc);
+ retval = FAIL;
+ goto out;
+ }
if (!mrsas_get_map_info(sc))
mrsas_sync_map_info(sc);
+ mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
+ mrsas_enable_intr(sc);
+ sc->adprecovery = MRSAS_HBA_OPERATIONAL;
+
/* Adapter reset completed successfully */
device_printf(sc->mrsas_dev, "Reset successful\n");
retval = SUCCESS;
@@ -2853,11 +2888,43 @@ out:
void
mrsas_kill_hba(struct mrsas_softc *sc)
{
+ sc->adprecovery = MRSAS_HW_CRITICAL_ERROR;
+ pause("mrsas_kill_hba", 1000);
mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__);
mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell),
MFI_STOP_ADP);
/* Flush */
mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell));
+ mrsas_complete_outstanding_ioctls(sc);
+}
+
+/**
+ * mrsas_complete_outstanding_ioctls Complete pending IOCTLS after kill_hba
+ * input: Controller softc
+ *
+ * Returns void
+ */
+void
+mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc)
+{
+ int i;
+ struct mrsas_mpt_cmd *cmd_mpt;
+ struct mrsas_mfi_cmd *cmd_mfi;
+ u_int32_t count, MSIxIndex;
+
+ count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
+ for (i = 0; i < sc->max_fw_cmds; i++) {
+ cmd_mpt = sc->mpt_cmd_list[i];
+
+ if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
+ cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
+ if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) {
+ for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
+ mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
+ cmd_mpt->io_request->RaidContext.status);
+ }
+ }
+ }
}
/*
@@ -2944,8 +3011,7 @@ mrsas_release_mfi_cmd(struct mrsas_mfi_c
* supported by the FW.
*/
static int
-mrsas_get_ctrl_info(struct mrsas_softc *sc,
- struct mrsas_ctrl_info *ctrl_info)
+mrsas_get_ctrl_info(struct mrsas_softc *sc)
{
int retcode = 0;
struct mrsas_mfi_cmd *cmd;
@@ -2978,16 +3044,60 @@ mrsas_get_ctrl_info(struct mrsas_softc *
dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info);
if (!mrsas_issue_polled(sc, cmd))
- memcpy(ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
+ memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
else
retcode = 1;
+ mrsas_update_ext_vd_details(sc);
+
mrsas_free_ctlr_info_cmd(sc);
mrsas_release_mfi_cmd(cmd);
return (retcode);
}
/*
+ * mrsas_update_ext_vd_details : Update details w.r.t Extended VD
+ * input:
+ * sc - Controller's softc
+*/
+static void
+mrsas_update_ext_vd_details(struct mrsas_softc *sc)
+{
+ sc->max256vdSupport =
+ sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
+ /* Below is additional check to address future FW enhancement */
+ if (sc->ctrl_info->max_lds > 64)
+ sc->max256vdSupport = 1;
+
+ sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS
+ * MRSAS_MAX_DEV_PER_CHANNEL;
+ sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS
+ * MRSAS_MAX_DEV_PER_CHANNEL;
+ if (sc->max256vdSupport) {
+ sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
+ sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
+ } else {
+ sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
+ sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
+ }
+
+ sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
+ (sizeof(MR_LD_SPAN_MAP) *
+ (sc->fw_supported_vd_count - 1));
+ sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
+ sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) +
+ (sizeof(MR_LD_SPAN_MAP) *
+ (sc->drv_supported_vd_count - 1));
+
+ sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
+
+ if (sc->max256vdSupport)
+ sc->current_map_sz = sc->new_map_sz;
+ else
+ sc->current_map_sz = sc->old_map_sz;
+}
+
+/*
* mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command
* input: Adapter soft state
*
@@ -3762,7 +3872,7 @@ mrsas_get_ld_list(struct mrsas_softc *sc
* memory is initialized to all zeros upon successful loading of the dma
* mapped memory.
*/
-int
+int
mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc,
struct mrsas_tmp_dcmd *tcmd, int size)
{
@@ -3995,10 +4105,12 @@ mrsas_complete_aen(struct mrsas_softc *s
*/
if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) {
sc->mrsas_aen_triggered = 1;
+ mtx_lock(&sc->aen_lock);
if (sc->mrsas_poll_waiting) {
sc->mrsas_poll_waiting = 0;
selwakeup(&sc->mrsas_select);
}
+ mtx_unlock(&sc->aen_lock);
} else
cmd->abort_aen = 0;
Modified: stable/10/sys/dev/mrsas/mrsas.h
==============================================================================
--- stable/10/sys/dev/mrsas/mrsas.h Thu Jun 11 14:02:23 2015 (r284266)
+++ stable/10/sys/dev/mrsas/mrsas.h Thu Jun 11 14:11:41 2015 (r284267)
@@ -1,6 +1,7 @@
/*
+ * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
* Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
- * Support: freebsdraid at lsi.com
+ * Support: freebsdraid at avagotech.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -31,7 +32,7 @@
* those of the authors and should not be interpreted as representing
* official policies,either expressed or implied, of the FreeBSD Project.
*
- * Send feedback to: <megaraidfbsd at lsi.com> Mail to: LSI Corporation, 1621
+ * Send feedback to: <megaraidfbsd at avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
* Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
*
*/
@@ -101,7 +102,7 @@ __FBSDID("$FreeBSD$");
*/
#define BYTE_ALIGNMENT 1
#define MRSAS_MAX_NAME_LENGTH 32
-#define MRSAS_VERSION "06.705.10.02-fbsd"
+#define MRSAS_VERSION "06.707.04.03-fbsd"
#define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
#define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */
#define DONE 0
@@ -813,9 +814,8 @@ typedef struct _MR_DRV_RAID_MAP_ALL {
typedef struct _LD_LOAD_BALANCE_INFO {
u_int8_t loadBalanceFlag;
u_int8_t reserved1;
- u_int16_t raid1DevHandle[2];
- mrsas_atomic_t scsi_pending_cmds[2];
- u_int64_t last_accessed_block[2];
+ mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
+ u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
/* SPAN_SET is info caclulated from span info from Raid map per ld */
@@ -858,6 +858,9 @@ struct IO_REQUEST_INFO {
u_int8_t start_span;
u_int8_t reserved;
u_int64_t start_row;
+ /* span[7:5], arm[4:0] */
+ u_int8_t span_arm;
+ u_int8_t pd_after_lb;
};
typedef struct _MR_LD_TARGET_SYNC {
@@ -1315,6 +1318,13 @@ typedef enum _REGION_TYPE {
#define MRSAS_REQ_STATE_TRAN 2
#define MRSAS_REQ_STATE_COMPLETE 3
+typedef enum _MR_SCSI_CMD_TYPE {
+ READ_WRITE_LDIO = 0,
+ NON_READ_WRITE_LDIO = 1,
+ READ_WRITE_SYSPDIO = 2,
+ NON_READ_WRITE_SYSPDIO = 3,
+} MR_SCSI_CMD_TYPE;
+
enum mrsas_req_flags {
MRSAS_DIR_UNKNOWN = 0x1,
MRSAS_DIR_IN = 0x2,
@@ -1350,6 +1360,7 @@ struct mrsas_mpt_cmd {
u_int32_t sync_cmd_idx;
u_int32_t index;
u_int8_t flags;
+ u_int8_t pd_r1_lb;
u_int8_t load_balance;
bus_size_t length;
u_int32_t error_code;
@@ -1897,9 +1908,26 @@ struct mrsas_ctrl_info {
char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */
struct { /* 0x7E8 */
- u_int32_t resrved:5;
+ u_int32_t supportPersonalityChange:2;
+ u_int32_t supportThermalPollInterval:1;
+ u_int32_t supportDisableImmediateIO:1;
+ u_int32_t supportT10RebuildAssist:1;
u_int32_t supportMaxExtLDs:1;
- u_int32_t reserved1:26;
+ u_int32_t supportCrashDump:1;
+ u_int32_t supportSwZone:1;
+ u_int32_t supportDebugQueue:1;
+ u_int32_t supportNVCacheErase:1;
+ u_int32_t supportForceTo512e:1;
+ u_int32_t supportHOQRebuild:1;
+ u_int32_t supportAllowedOpsforDrvRemoval:1;
+ u_int32_t supportDrvActivityLEDSetting:1;
+ u_int32_t supportNVDRAM:1;
+ u_int32_t supportForceFlash:1;
+ u_int32_t supportDisableSESMonitoring:1;
+ u_int32_t supportCacheBypassModes:1;
+ u_int32_t supportSecurityonJBOD:1;
+ u_int32_t discardCacheDuringLDDelete:1;
+ u_int32_t reserved:12;
} adapterOperations3;
u_int8_t pad[0x800 - 0x7EC]; /* 0x7EC */
@@ -1970,7 +1998,10 @@ typedef union _MFI_CAPABILITIES {
u_int32_t support_additional_msix:1;
u_int32_t support_fastpath_wb:1;
u_int32_t support_max_255lds:1;
- u_int32_t reserved:28;
+ u_int32_t support_ndrive_r1_lb:1;
+ u_int32_t support_core_affinity:1;
+ u_int32_t security_protocol_cmds_fw:1;
+ u_int32_t reserved:25;
} mfi_capabilities;
u_int32_t reg;
} MFI_CAPABILITIES;
@@ -2413,6 +2444,167 @@ struct mrsas_mgmt_info {
int max_index;
};
+#define PCI_TYPE0_ADDRESSES 6
+#define PCI_TYPE1_ADDRESSES 2
+#define PCI_TYPE2_ADDRESSES 5
+
+typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
+ u_int16_t vendorID;
+ //(ro)
+ u_int16_t deviceID;
+ //(ro)
+ u_int16_t command;
+ //Device control
+ u_int16_t status;
+ u_int8_t revisionID;
+ //(ro)
+ u_int8_t progIf;
+ //(ro)
+ u_int8_t subClass;
+ //(ro)
+ u_int8_t baseClass;
+ //(ro)
+ u_int8_t cacheLineSize;
+ //(ro +)
+ u_int8_t latencyTimer;
+ //(ro +)
+ u_int8_t headerType;
+ //(ro)
+ u_int8_t bist;
+ //Built in self test
+
+ union {
+ struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
+ u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
+ u_int32_t cis;
+ u_int16_t subVendorID;
+ u_int16_t subSystemID;
+ u_int32_t romBaseAddress;
+ u_int8_t capabilitiesPtr;
+ u_int8_t reserved1[3];
+ u_int32_t reserved2;
+ u_int8_t interruptLine;
+ u_int8_t interruptPin;
+ //(ro)
+ u_int8_t minimumGrant;
+ //(ro)
+ u_int8_t maximumLatency;
+ //(ro)
+ } type0;
+
+ /*
+ * PCI to PCI Bridge
+ */
+
+ struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
+ u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
+ u_int8_t primaryBus;
+ u_int8_t secondaryBus;
+ u_int8_t subordinateBus;
+ u_int8_t secondaryLatency;
+ u_int8_t ioBase;
+ u_int8_t ioLimit;
+ u_int16_t secondaryStatus;
+ u_int16_t memoryBase;
+ u_int16_t memoryLimit;
+ u_int16_t prefetchBase;
+ u_int16_t prefetchLimit;
+ u_int32_t prefetchBaseUpper32;
+ u_int32_t prefetchLimitUpper32;
+ u_int16_t ioBaseUpper16;
+ u_int16_t ioLimitUpper16;
+ u_int8_t capabilitiesPtr;
+ u_int8_t reserved1[3];
+ u_int32_t romBaseAddress;
+ u_int8_t interruptLine;
+ u_int8_t interruptPin;
+ u_int16_t bridgeControl;
+ } type1;
+
+ /*
+ * PCI to CARDBUS Bridge
+ */
+
+ struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
+ u_int32_t socketRegistersBaseAddress;
+ u_int8_t capabilitiesPtr;
+ u_int8_t reserved;
+ u_int16_t secondaryStatus;
+ u_int8_t primaryBus;
+ u_int8_t secondaryBus;
+ u_int8_t subordinateBus;
+ u_int8_t secondaryLatency;
+ struct {
+ u_int32_t base;
+ u_int32_t limit;
+ } range [PCI_TYPE2_ADDRESSES - 1];
+ u_int8_t interruptLine;
+ u_int8_t interruptPin;
+ u_int16_t bridgeControl;
+ } type2;
+ } u;
+
+} MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
+
+#define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes
+
+typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
+ union {
+ struct {
+ u_int32_t linkSpeed:4;
+ u_int32_t linkWidth:6;
+ u_int32_t aspmSupport:2;
+ u_int32_t losExitLatency:3;
+ u_int32_t l1ExitLatency:3;
+ u_int32_t rsvdp:6;
+ u_int32_t portNumber:8;
+ } bits;
+
+ u_int32_t asUlong;
+ } u;
+} MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
+
+#define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
+
+typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
+ union {
+ struct {
+ u_int16_t linkSpeed:4;
+ u_int16_t negotiatedLinkWidth:6;
+ u_int16_t linkTrainingError:1;
+ u_int16_t linkTraning:1;
+ u_int16_t slotClockConfig:1;
+ u_int16_t rsvdZ:3;
+ } bits;
+
+ u_int16_t asUshort;
+ } u;
+ u_int16_t reserved;
+} MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
+
+#define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
+
+
+typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
+ MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
+ MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
+} MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
+
+#define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
+
+/* PCI information */
+typedef struct _MRSAS_DRV_PCI_INFORMATION {
+ u_int32_t busNumber;
+ u_int8_t deviceNumber;
+ u_int8_t functionNumber;
+ u_int8_t interruptVector;
+ u_int8_t reserved1;
+ MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
+ MRSAS_DRV_PCI_CAPABILITIES capability;
+ u_int32_t domainID;
+ u_int8_t reserved2[28];
+} MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
+
/*******************************************************************
* per-instance data
********************************************************************/
@@ -2476,6 +2668,7 @@ struct mrsas_softc {
int msix_vectors;
int msix_enable;
uint32_t msix_reg_offset[16];
+ uint8_t mask_interrupts;
struct mrsas_mpt_cmd **mpt_cmd_list;
struct mrsas_mfi_cmd **mfi_cmd_list;
TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
@@ -2519,6 +2712,7 @@ struct mrsas_softc {
bus_dmamap_t evt_detail_dmamap;
struct mrsas_evt_detail *evt_detail_mem;
bus_addr_t evt_detail_phys_addr;
+ struct mrsas_ctrl_info *ctrl_info;
bus_dma_tag_t ctlr_info_tag;
bus_dmamap_t ctlr_info_dmamap;
void *ctlr_info_mem;
@@ -2546,9 +2740,11 @@ struct mrsas_softc {
struct task ev_task;
u_int32_t CurLdCount;
u_int64_t reset_flags;
+ int lb_pending_cmds;
LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
+ u_int8_t secure_jbod_support;
u_int8_t max256vdSupport;
u_int16_t fw_supported_vd_count;
u_int16_t fw_supported_pd_count;
Modified: stable/10/sys/dev/mrsas/mrsas_cam.c
==============================================================================
--- stable/10/sys/dev/mrsas/mrsas_cam.c Thu Jun 11 14:02:23 2015 (r284266)
+++ stable/10/sys/dev/mrsas/mrsas_cam.c Thu Jun 11 14:11:41 2015 (r284267)
@@ -1,6 +1,7 @@
/*
+ * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy
* Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
- * Support: freebsdraid at lsi.com
+ * Support: freebsdraid at avagotech.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -57,17 +58,19 @@ __FBSDID("$FreeBSD$");
* Function prototypes
*/
int mrsas_cam_attach(struct mrsas_softc *sc);
-int mrsas_ldio_inq(struct cam_sim *sim, union ccb *ccb);
+int mrsas_find_io_type(struct cam_sim *sim, union ccb *ccb);
int mrsas_bus_scan(struct mrsas_softc *sc);
int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim);
-int mrsas_map_request(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);
int
+mrsas_map_request(struct mrsas_softc *sc,
+ struct mrsas_mpt_cmd *cmd, union ccb *ccb);
+int
mrsas_build_ldio(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
union ccb *ccb);
-int
+int
mrsas_build_dcdb(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
union ccb *ccb, struct cam_sim *sim);
-int
+int
mrsas_setup_io(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
union ccb *ccb, u_int32_t device_id,
MRSAS_RAID_SCSI_IO_REQUEST * io_request);
@@ -77,10 +80,10 @@ void mrsas_cam_detach(struct mrsas_softc
void mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd);
void mrsas_unmap_request(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);
void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);
-void
+void
mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
u_int32_t req_desc_hi);
-void
+void
mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request,
u_int8_t cdb_len, struct IO_REQUEST_INFO *io_info, union ccb *ccb,
MR_DRV_RAID_MAP_ALL * local_map_ptr, u_int32_t ref_tag,
@@ -89,10 +92,10 @@ static void mrsas_freeze_simq(struct mrs
static void mrsas_cam_poll(struct cam_sim *sim);
static void mrsas_action(struct cam_sim *sim, union ccb *ccb);
static void mrsas_scsiio_timeout(void *data);
-static void
+static void
mrsas_data_load_cb(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
-static int32_t
+static int32_t
mrsas_startio(struct mrsas_softc *sc, struct cam_sim *sim,
union ccb *ccb);
struct mrsas_mpt_cmd *mrsas_get_mpt_cmd(struct mrsas_softc *sc);
@@ -112,9 +115,9 @@ MR_BuildRaidContext(struct mrsas_softc *
extern u_int16_t
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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