svn commit: r277900 - head/sys/x86/x86

[John Baldwin]

On Thursday, January 29, 2015 08:41:43 PM John Baldwin wrote:
> Author: jhb
> Date: Thu Jan 29 20:41:42 2015
> New Revision: 277900
> URL: https://svnweb.freebsd.org/changeset/base/277900
> 
> Log:
>   Opt for performance over power-saving on Intel CPUs that have a
>   P-state but not C-state invariant TSC by changing the default behavior
>   to leaving the TSC enabled as the timecounter and disabling C2+ instead
>   of disabling the TSC by default.
> 
>   Discussed with:		jkim
>   Tested by:		Jan Kokemuller <jan.kokemueller at gmail.com>

Note that C1E remains enabled and in my experience that often gives the
largest gain in power saving (that is, the delta between C1E and C2 is
much smaller than the gain of plain C1 to C1E).

Also, note that we always use the TSC as the cpu ticker, even if it is not the 
timecounter.  Thus, if C2+ is enabled on the systems, the kernel idle threads 
will have an artificially low runtime since their idle time is not properly 
accounted for.  This does not affect any other threads as only the idle 
threads "run" while the CPU is in C2+ with the TSC effectively paused.  The 
new default means that the idle threads will now have the proper runtime, 
however.

-- 
John Baldwin