svn commit: r277220 - in vendor/llvm/dist: . autoconf cmake/modules docs include/llvm/Analysis include/llvm/CodeGen include/llvm/Target lib/Analysis lib/MC lib/Target/ARM lib/Target/Mips lib/Target...

Dimitry Andric dim at FreeBSD.org
Thu Jan 15 22:30:22 UTC 2015


Author: dim
Date: Thu Jan 15 22:30:16 2015
New Revision: 277220
URL: https://svnweb.freebsd.org/changeset/base/277220

Log:
  Vendor import of llvm RELEASE_351/final tag r225668 (effectively, 3.5.1 release):
  https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_351/final@225668

Added:
  vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.cpp   (contents, props changed)
  vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.h   (contents, props changed)
  vendor/llvm/dist/lib/Target/Mips/MipsCCState.cpp   (contents, props changed)
  vendor/llvm/dist/lib/Target/Mips/MipsCCState.h   (contents, props changed)
  vendor/llvm/dist/test/Analysis/BlockFrequencyInfo/extremely-likely-loop-successor.ll
  vendor/llvm/dist/test/CodeGen/ARM/ghc-tcreturn-lowered.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-struct.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-varargs.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/return-struct.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/blockaddress.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/ia-mem-r0.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/ia-neg-const.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/subreg-postra-2.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/subreg-postra.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/tls-store2.ll
  vendor/llvm/dist/test/MC/Disassembler/Mips/mips2.txt   (contents, props changed)
  vendor/llvm/dist/test/Transforms/IndVarSimplify/pr20680.ll
  vendor/llvm/dist/test/Transforms/LICM/PR21582.ll
  vendor/llvm/dist/test/Transforms/LoopVectorize/incorrect-dom-info.ll
  vendor/llvm/dist/test/Transforms/LoopVectorize/loop-form.ll
  vendor/llvm/dist/test/Transforms/LoopVectorize/unsized-pointee-crash.ll
Modified:
  vendor/llvm/dist/CMakeLists.txt
  vendor/llvm/dist/autoconf/configure.ac
  vendor/llvm/dist/cmake/modules/Makefile
  vendor/llvm/dist/configure
  vendor/llvm/dist/docs/ReleaseNotes.rst
  vendor/llvm/dist/include/llvm/Analysis/AliasSetTracker.h
  vendor/llvm/dist/include/llvm/CodeGen/CallingConvLower.h
  vendor/llvm/dist/include/llvm/Target/TargetCallingConv.td
  vendor/llvm/dist/lib/Analysis/AliasSetTracker.cpp
  vendor/llvm/dist/lib/Analysis/BlockFrequencyInfoImpl.cpp
  vendor/llvm/dist/lib/Analysis/ValueTracking.cpp
  vendor/llvm/dist/lib/MC/MCObjectFileInfo.cpp
  vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.cpp
  vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.h
  vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp
  vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  vendor/llvm/dist/lib/Target/Mips/CMakeLists.txt
  vendor/llvm/dist/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  vendor/llvm/dist/lib/Target/Mips/Mips.td
  vendor/llvm/dist/lib/Target/Mips/Mips16ISelLowering.cpp
  vendor/llvm/dist/lib/Target/Mips/Mips16ISelLowering.h
  vendor/llvm/dist/lib/Target/Mips/Mips64InstrInfo.td
  vendor/llvm/dist/lib/Target/Mips/MipsAsmPrinter.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsCallingConv.td
  vendor/llvm/dist/lib/Target/Mips/MipsConstantIslandPass.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h
  vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td
  vendor/llvm/dist/lib/Target/Mips/MipsInstrInfo.td
  vendor/llvm/dist/lib/Target/Mips/MipsLongBranch.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsRegisterInfo.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsSEFrameLowering.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsSEISelLowering.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsSEISelLowering.h
  vendor/llvm/dist/lib/Target/Mips/MipsSubtarget.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsSubtarget.h
  vendor/llvm/dist/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
  vendor/llvm/dist/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
  vendor/llvm/dist/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPC.h
  vendor/llvm/dist/lib/Target/PowerPC/PPCAsmPrinter.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCFastISel.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.h
  vendor/llvm/dist/lib/Target/PowerPC/PPCInstr64Bit.td
  vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.td
  vendor/llvm/dist/lib/Target/PowerPC/PPCMCInstLower.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCRegisterInfo.td
  vendor/llvm/dist/lib/Target/X86/X86FastISel.cpp
  vendor/llvm/dist/lib/Transforms/Scalar/IndVarSimplify.cpp
  vendor/llvm/dist/lib/Transforms/Scalar/MergedLoadStoreMotion.cpp
  vendor/llvm/dist/lib/Transforms/Scalar/SROA.cpp
  vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp
  vendor/llvm/dist/test/CodeGen/Mips/abicalls.ll
  vendor/llvm/dist/test/CodeGen/Mips/atomic.ll
  vendor/llvm/dist/test/CodeGen/Mips/bswap.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-float.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/return-float.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/return-hard-float.ll
  vendor/llvm/dist/test/CodeGen/Mips/cconv/return.ll
  vendor/llvm/dist/test/CodeGen/Mips/cmov.ll
  vendor/llvm/dist/test/CodeGen/Mips/const-mult.ll
  vendor/llvm/dist/test/CodeGen/Mips/countleading.ll
  vendor/llvm/dist/test/CodeGen/Mips/divrem.ll
  vendor/llvm/dist/test/CodeGen/Mips/ehframe-indirect.ll
  vendor/llvm/dist/test/CodeGen/Mips/fastcc.ll
  vendor/llvm/dist/test/CodeGen/Mips/fp64a.ll
  vendor/llvm/dist/test/CodeGen/Mips/inlineasm-operand-code.ll
  vendor/llvm/dist/test/CodeGen/Mips/load-store-left-right.ll
  vendor/llvm/dist/test/CodeGen/Mips/longbranch.ll
  vendor/llvm/dist/test/CodeGen/Mips/madd-msub.ll
  vendor/llvm/dist/test/CodeGen/Mips/mips64-f128.ll
  vendor/llvm/dist/test/CodeGen/Mips/mips64-sret.ll
  vendor/llvm/dist/test/CodeGen/Mips/msa/frameindex.ll
  vendor/llvm/dist/test/CodeGen/Mips/octeon_popcnt.ll
  vendor/llvm/dist/test/CodeGen/Mips/select.ll
  vendor/llvm/dist/test/CodeGen/Mips/zeroreg.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/cc.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/fast-isel-conversion.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/fast-isel-ret.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/stack-realign.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/tls-pic.ll
  vendor/llvm/dist/test/MC/Disassembler/Mips/mips32.txt
  vendor/llvm/dist/test/MC/Disassembler/Mips/mips64.txt
  vendor/llvm/dist/test/MC/PowerPC/ppc64-localentry.s
  vendor/llvm/dist/test/Transforms/GCOVProfiling/linezero.ll
  vendor/llvm/dist/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
  vendor/llvm/dist/test/Transforms/IndVarSimplify/lftr-address-space-pointers.ll
  vendor/llvm/dist/test/Transforms/IndVarSimplify/lftr-extend-const.ll
  vendor/llvm/dist/test/Transforms/IndVarSimplify/lftr-reuse.ll
  vendor/llvm/dist/test/Transforms/LICM/speculate.ll
  vendor/llvm/dist/test/Transforms/LoopVectorize/runtime-check-address-space.ll
  vendor/llvm/dist/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
  vendor/llvm/dist/test/Transforms/LoopVectorize/vect.stats.ll
  vendor/llvm/dist/test/Transforms/SROA/phi-and-select.ll
  vendor/llvm/dist/unittests/Analysis/LazyCallGraphTest.cpp
  vendor/llvm/dist/utils/TableGen/CallingConvEmitter.cpp
  vendor/llvm/dist/utils/lit/lit/Test.py
  vendor/llvm/dist/utils/lit/lit/main.py

Modified: vendor/llvm/dist/CMakeLists.txt
==============================================================================
--- vendor/llvm/dist/CMakeLists.txt	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/CMakeLists.txt	Thu Jan 15 22:30:16 2015	(r277220)
@@ -27,7 +27,7 @@ set(CMAKE_MODULE_PATH
 
 set(LLVM_VERSION_MAJOR 3)
 set(LLVM_VERSION_MINOR 5)
-set(LLVM_VERSION_PATCH 0)
+set(LLVM_VERSION_PATCH 1)
 
 if (NOT PACKAGE_VERSION)
   set(PACKAGE_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}svn")

Modified: vendor/llvm/dist/autoconf/configure.ac
==============================================================================
--- vendor/llvm/dist/autoconf/configure.ac	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/autoconf/configure.ac	Thu Jan 15 22:30:16 2015	(r277220)
@@ -32,11 +32,11 @@ dnl===----------------------------------
 dnl Initialize autoconf and define the package name, version number and
 dnl address for reporting bugs.
 
-AC_INIT([LLVM],[3.5.0],[http://llvm.org/bugs/])
+AC_INIT([LLVM],[3.5.1],[http://llvm.org/bugs/])
 
 LLVM_VERSION_MAJOR=3
 LLVM_VERSION_MINOR=5
-LLVM_VERSION_PATCH=0
+LLVM_VERSION_PATCH=1
 LLVM_VERSION_SUFFIX=
 
 AC_DEFINE_UNQUOTED([LLVM_VERSION_MAJOR], $LLVM_VERSION_MAJOR, [Major version of the LLVM API])

Modified: vendor/llvm/dist/cmake/modules/Makefile
==============================================================================
--- vendor/llvm/dist/cmake/modules/Makefile	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/cmake/modules/Makefile	Thu Jan 15 22:30:16 2015	(r277220)
@@ -33,6 +33,19 @@ else
 	LLVM_ENABLE_RTTI := 0
 endif
 
+# Don't try to run llvm-config during clean because it won't be available
+ifneq ($(MAKECMDGOALS),clean)
+LLVM_LIBS_TO_EXPORT := $(subst -l,,$(shell $(LLVM_CONFIG) --libs $(LINK_COMPONENTS) || echo Error))
+
+ifeq ($(LLVM_LIBS_TO_EXPORT),Error)
+$(error llvm-config --libs failed)
+endif
+
+ifndef LLVM_LIBS_TO_EXPORT
+$(error LLVM_LIBS_TO_EXPORT cannot be empty)
+endif
+endif
+
 OBJMODS := LLVMConfig.cmake LLVMConfigVersion.cmake LLVMExports.cmake
 
 $(PROJ_OBJ_DIR)/LLVMConfig.cmake: LLVMConfig.cmake.in $(LLVMBuildCMakeFrag)
@@ -45,7 +58,7 @@ $(PROJ_OBJ_DIR)/LLVMConfig.cmake: LLVMCo
 	  -e 's/@LLVM_VERSION_PATCH@/'"$(LLVM_VERSION_PATCH)"'/' \
 	  -e 's/@PACKAGE_VERSION@/'"$(LLVMVersion)"'/' \
 	  -e 's/@LLVM_COMMON_DEPENDS@//' \
-	  -e 's/@LLVM_AVAILABLE_LIBS@/'"$(subst -l,,$(LLVMConfigLibs))"'/' \
+	  -e 's/@LLVM_AVAILABLE_LIBS@/'"$(LLVM_LIBS_TO_EXPORT)"'/' \
 	  -e 's/@LLVM_ALL_TARGETS@/'"$(ALL_TARGETS)"'/' \
 	  -e 's/@LLVM_TARGETS_TO_BUILD@/'"$(TARGETS_TO_BUILD)"'/' \
 	  -e 's/@LLVM_TARGETS_WITH_JIT@/'"$(TARGETS_WITH_JIT)"'/' \
@@ -83,7 +96,7 @@ $(PROJ_OBJ_DIR)/LLVMExports.cmake: $(LLV
 	$(Echo) 'Generating LLVM CMake target exports file'
 	$(Verb) ( \
 	  echo '# LLVM CMake target exports.  Do not include directly.' && \
-	  for lib in $(subst -l,,$(LLVMConfigLibs)); do \
+	  for lib in $(LLVM_LIBS_TO_EXPORT); do \
 	    echo 'add_library('"$$lib"' STATIC IMPORTED)' && \
 	    echo 'set_property(TARGET '"$$lib"' PROPERTY IMPORTED_LOCATION "'"$(PROJ_libdir)/lib$$lib.a"'")' ; \
 	  done && \

Modified: vendor/llvm/dist/configure
==============================================================================
--- vendor/llvm/dist/configure	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/configure	Thu Jan 15 22:30:16 2015	(r277220)
@@ -1,6 +1,6 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.60 for LLVM 3.5.0.
+# Generated by GNU Autoconf 2.60 for LLVM 3.5.1.
 #
 # Report bugs to <http://llvm.org/bugs/>.
 #
@@ -561,8 +561,8 @@ SHELL=${CONFIG_SHELL-/bin/sh}
 # Identity of this package.
 PACKAGE_NAME='LLVM'
 PACKAGE_TARNAME='llvm'
-PACKAGE_VERSION='3.5.0'
-PACKAGE_STRING='LLVM 3.5.0'
+PACKAGE_VERSION='3.5.1'
+PACKAGE_STRING='LLVM 3.5.1'
 PACKAGE_BUGREPORT='http://llvm.org/bugs/'
 
 ac_unique_file="lib/IR/Module.cpp"
@@ -1316,7 +1316,7 @@ if test "$ac_init_help" = "long"; then
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF
-\`configure' configures LLVM 3.5.0 to adapt to many kinds of systems.
+\`configure' configures LLVM 3.5.1 to adapt to many kinds of systems.
 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 
@@ -1382,7 +1382,7 @@ fi
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in
-     short | recursive ) echo "Configuration of LLVM 3.5.0:";;
+     short | recursive ) echo "Configuration of LLVM 3.5.1:";;
    esac
   cat <<\_ACEOF
 
@@ -1553,7 +1553,7 @@ fi
 test -n "$ac_init_help" && exit $ac_status
 if $ac_init_version; then
   cat <<\_ACEOF
-LLVM configure 3.5.0
+LLVM configure 3.5.1
 generated by GNU Autoconf 2.60
 
 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
@@ -1569,7 +1569,7 @@ cat >config.log <<_ACEOF
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
-It was created by LLVM $as_me 3.5.0, which was
+It was created by LLVM $as_me 3.5.1, which was
 generated by GNU Autoconf 2.60.  Invocation command line was
 
   $ $0 $@
@@ -1925,7 +1925,7 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
 
 LLVM_VERSION_MAJOR=3
 LLVM_VERSION_MINOR=5
-LLVM_VERSION_PATCH=0
+LLVM_VERSION_PATCH=1
 LLVM_VERSION_SUFFIX=
 
 
@@ -19245,7 +19245,7 @@ exec 6>&1
 # report actual input values of CONFIG_FILES etc. instead of their
 # values after options handling.
 ac_log="
-This file was extended by LLVM $as_me 3.5.0, which was
+This file was extended by LLVM $as_me 3.5.1, which was
 generated by GNU Autoconf 2.60.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
@@ -19298,7 +19298,7 @@ Report bugs to <bug-autoconf at gnu.org>."
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF
 ac_cs_version="\\
-LLVM config.status 3.5.0
+LLVM config.status 3.5.1
 configured by $0, generated by GNU Autoconf 2.60,
   with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
 

Modified: vendor/llvm/dist/docs/ReleaseNotes.rst
==============================================================================
--- vendor/llvm/dist/docs/ReleaseNotes.rst	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/docs/ReleaseNotes.rst	Thu Jan 15 22:30:16 2015	(r277220)
@@ -24,6 +24,43 @@ them.
 Non-comprehensive list of changes in this release
 =================================================
 
+Changes to the MIPS Target
+--------------------------
+
+* A large number of bugs have been fixed for big-endian Mips targets using the
+  N32 and N64 ABI's. Please note that some of these bugs will still affect
+  LLVM-IR generated by LLVM 3.5 since correct code generation depends on
+  appropriate usage of the ``inreg``, ``signext``, and ``zeroext`` attributes
+  on all function arguments and returns.
+
+* The registers used to return a structure containing a single 128-bit floating
+  point member on the N32/N64 ABI's have been changed from those specified by
+  the ABI documentation to match those used by GCC. The documentation specifies
+  that ``$f0`` and ``$f2`` should be used but GCC has used ``$f0`` and ``$f1``
+  for many years.
+
+* Returning a zero-byte struct no longer causes incorrect code generation when
+  using the O32 ABI.
+
+* Passing structures of less than 32-bits using the O32 ABI on a big-endian
+  target has been fixed.
+
+* The exception personality has been changed for 64-bit Mips targets to
+  eliminate warnings about relocations in a read-only section.
+
+* Incorrect usage of odd-numbered single-precision floating point registers
+  has been fixed when the fastcc calling convention is used with 64-bit FPU's
+  and -mno-odd-spreg.
+
+* For inline assembly, the 'z' print-modifier print modifier can now be used on
+  non-immediate values.
+
+* Attempting to disassemble l[wd]c[23], s[wd]c[23], cache, and pref no longer
+  triggers an assertion.
+
+Non-comprehensive list of changes in 3.5
+========================================
+
 * All backends have been changed to use the MC asm printer and support for the
   non MC one has been removed.
 
@@ -217,6 +254,37 @@ We had also decided that the name of the
 following ARM's official documentation. So, at the end of May the old
 AArch64 directory was removed, and ARM64 renamed into its place.
 
+Changes to the PowerPC Target
+-----------------------------
+
+The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is
+now fully supported.  This includes support for the Altivec instruction set.
+
+The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and
+is the default ABI for Little Endian.  The ELFv1 ABI remains the default ABI
+for Big Endian.  Currently, it is not possible to override these defaults.
+That capability will be available (albeit not recommended) in a future release.
+
+Links to the ELFv2 ABI specification and to the Power ISA Version 2.07
+specification may be found `here <https://www-03.ibm.com/technologyconnect/tgcm/TGCMServlet.wss?alias=OpenPOWER&linkid=1n0000>`_ (free registration required).
+Efforts are underway to move this to a location that doesn't require
+registration, but the planned site isn't ready yet.
+
+Experimental support for the VSX instruction set introduced with ISA 2.06
+is now available using the ``-mvsx`` switch.  Work remains on this, so it
+is not recommended for production use.  VSX is disabled for Little Endian
+regardless of this switch setting.
+
+Load/store cost estimates have been improved.
+
+Constant hoisting has been enabled.
+
+Global named register support has been enabled.
+
+Initial support for PIC code has been added for the 32-bit ELF subtarget.
+Further support will be available in a future release.
+
+
 Changes to CMake build system
 -----------------------------
 

Modified: vendor/llvm/dist/include/llvm/Analysis/AliasSetTracker.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/AliasSetTracker.h	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/include/llvm/Analysis/AliasSetTracker.h	Thu Jan 15 22:30:16 2015	(r277220)
@@ -253,13 +253,16 @@ private:
                   const MDNode *TBAAInfo,
                   bool KnownMustAlias = false);
   void addUnknownInst(Instruction *I, AliasAnalysis &AA);
-  void removeUnknownInst(Instruction *I) {
+  void removeUnknownInst(AliasSetTracker &AST, Instruction *I) {
+    bool WasEmpty = UnknownInsts.empty();
     for (size_t i = 0, e = UnknownInsts.size(); i != e; ++i)
       if (UnknownInsts[i] == I) {
         UnknownInsts[i] = UnknownInsts.back();
         UnknownInsts.pop_back();
         --i; --e;  // Revisit the moved entry.
       }
+    if (!WasEmpty && UnknownInsts.empty())
+      dropRef(AST);
   }
   void setVolatile() { Volatile = true; }
 

Modified: vendor/llvm/dist/include/llvm/CodeGen/CallingConvLower.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/CallingConvLower.h	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/include/llvm/CodeGen/CallingConvLower.h	Thu Jan 15 22:30:16 2015	(r277220)
@@ -31,18 +31,25 @@ class TargetRegisterInfo;
 class CCValAssign {
 public:
   enum LocInfo {
-    Full,   // The value fills the full location.
-    SExt,   // The value is sign extended in the location.
-    ZExt,   // The value is zero extended in the location.
-    AExt,   // The value is extended with undefined upper bits.
-    BCvt,   // The value is bit-converted in the location.
-    VExt,   // The value is vector-widened in the location.
-            // FIXME: Not implemented yet. Code that uses AExt to mean
-            // vector-widen should be fixed to use VExt instead.
-    FPExt,  // The floating-point value is fp-extended in the location.
-    Indirect // The location contains pointer to the value.
+    Full,      // The value fills the full location.
+    SExt,      // The value is sign extended in the location.
+    ZExt,      // The value is zero extended in the location.
+    AExt,      // The value is extended with undefined upper bits.
+    BCvt,      // The value is bit-converted in the location.
+    VExt,      // The value is vector-widened in the location.
+               // FIXME: Not implemented yet. Code that uses AExt to mean
+               // vector-widen should be fixed to use VExt instead.
+    FPExt,     // The floating-point value is fp-extended in the location.
+    Indirect,  // The location contains pointer to the value.
+    SExtUpper, // The value is in the upper bits of the location and should be
+               // sign extended when retrieved.
+    ZExtUpper, // The value is in the upper bits of the location and should be
+               // zero extended when retrieved.
+    AExtUpper  // The value is in the upper bits of the location and should be
+               // extended with undefined upper bits when retrieved.
     // TODO: a subset of the value is in the location.
   };
+
 private:
   /// ValNo - This is the value number begin assigned (e.g. an argument number).
   unsigned ValNo;
@@ -146,6 +153,9 @@ public:
     return (HTP == AExt || HTP == SExt || HTP == ZExt);
   }
 
+  bool isUpperBitsInLoc() const {
+    return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
+  }
 };
 
 /// CCAssignFn - This function assigns a location for Val, updating State to
@@ -208,10 +218,10 @@ private:
   // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
   //
   // Supposed use-case for this collection:
-  // 1. Initially ByValRegs is empty, InRegsParamsProceed is 0.
+  // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
   // 2. HandleByVal fillups ByValRegs.
   // 3. Argument analysis (LowerFormatArguments, for example). After
-  // some byval argument was analyzed, InRegsParamsProceed is increased.
+  // some byval argument was analyzed, InRegsParamsProcessed is increased.
   struct ByValInfo {
     ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
       Begin(B), End(E), Waste(IsWaste) {}
@@ -229,9 +239,9 @@ private:
   };
   SmallVector<ByValInfo, 4 > ByValRegs;
 
-  // InRegsParamsProceed - shows how many instances of ByValRegs was proceed
+  // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
   // during argument analysis.
-  unsigned InRegsParamsProceed;
+  unsigned InRegsParamsProcessed;
 
 protected:
   ParmContext CallOrPrologue;
@@ -412,7 +422,7 @@ public:
   unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
 
   // Returns count of byval in-regs arguments proceed.
-  unsigned getInRegsParamsProceed() const { return InRegsParamsProceed; }
+  unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
 
   // Get information about N-th byval parameter that is stored in registers.
   // Here "ByValParamIndex" is N.
@@ -436,20 +446,20 @@ public:
   // Returns false, if end is reached.
   bool nextInRegsParam() {
     unsigned e = ByValRegs.size();
-    if (InRegsParamsProceed < e)
-      ++InRegsParamsProceed;
-    return InRegsParamsProceed < e;
+    if (InRegsParamsProcessed < e)
+      ++InRegsParamsProcessed;
+    return InRegsParamsProcessed < e;
   }
 
   // Clear byval registers tracking info.
   void clearByValRegsInfo() {
-    InRegsParamsProceed = 0;
+    InRegsParamsProcessed = 0;
     ByValRegs.clear();
   }
 
   // Rewind byval registers tracking info.
   void rewindByValRegsInfo() {
-    InRegsParamsProceed = 0;
+    InRegsParamsProcessed = 0;
   }
 
   ParmContext getCallOrPrologue() const { return CallOrPrologue; }

Modified: vendor/llvm/dist/include/llvm/Target/TargetCallingConv.td
==============================================================================
--- vendor/llvm/dist/include/llvm/Target/TargetCallingConv.td	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/include/llvm/Target/TargetCallingConv.td	Thu Jan 15 22:30:16 2015	(r277220)
@@ -67,6 +67,9 @@ class CCIfSplit<CCAction A> : CCIf<"ArgF
 /// the specified action.
 class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {}
 
+/// CCIfVarArg - If the current function is vararg - apply the action
+class CCIfVarArg<CCAction A> : CCIf<"State.isVarArg()", A> {}
+
 /// CCIfNotVarArg - If the current function is not vararg - apply the action
 class CCIfNotVarArg<CCAction A> : CCIf<"!State.isVarArg()", A> {}
 
@@ -119,6 +122,12 @@ class CCPromoteToType<ValueType destTy> 
   ValueType DestTy = destTy;
 }
 
+/// CCPromoteToUpperBitsInType - If applied, this promotes the specified current
+/// value to the specified type and shifts the value into the upper bits.
+class CCPromoteToUpperBitsInType<ValueType destTy> : CCAction {
+  ValueType DestTy = destTy;
+}
+
 /// CCBitConvertToType - If applied, this bitconverts the specified current
 /// value to the specified type.
 class CCBitConvertToType<ValueType destTy> : CCAction {
@@ -141,6 +150,13 @@ class CCDelegateTo<CallingConv cc> : CCA
 /// that the target supports.
 class CallingConv<list<CCAction> actions> {
   list<CCAction> Actions = actions;
+  bit Custom = 0;
+}
+
+/// CustomCallingConv - An instance of this is used to declare calling
+/// conventions that are implemented using a custom function of the same name.
+class CustomCallingConv : CallingConv<[]> {
+  let Custom = 1;
 }
 
 /// CalleeSavedRegs - A list of callee saved registers for a given calling

Modified: vendor/llvm/dist/lib/Analysis/AliasSetTracker.cpp
==============================================================================
--- vendor/llvm/dist/lib/Analysis/AliasSetTracker.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Analysis/AliasSetTracker.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -55,10 +55,13 @@ void AliasSet::mergeSetIn(AliasSet &AS, 
       AliasTy = MayAlias;
   }
 
+  bool ASHadUnknownInsts = !AS.UnknownInsts.empty();
   if (UnknownInsts.empty()) {            // Merge call sites...
-    if (!AS.UnknownInsts.empty())
+    if (ASHadUnknownInsts) {
       std::swap(UnknownInsts, AS.UnknownInsts);
-  } else if (!AS.UnknownInsts.empty()) {
+      addRef();
+    }
+  } else if (ASHadUnknownInsts) {
     UnknownInsts.insert(UnknownInsts.end(), AS.UnknownInsts.begin(), AS.UnknownInsts.end());
     AS.UnknownInsts.clear();
   }
@@ -76,6 +79,8 @@ void AliasSet::mergeSetIn(AliasSet &AS, 
     AS.PtrListEnd = &AS.PtrList;
     assert(*AS.PtrListEnd == nullptr && "End of list is not null?");
   }
+  if (ASHadUnknownInsts)
+    AS.dropRef(AST);
 }
 
 void AliasSetTracker::removeAliasSet(AliasSet *AS) {
@@ -123,6 +128,8 @@ void AliasSet::addPointer(AliasSetTracke
 }
 
 void AliasSet::addUnknownInst(Instruction *I, AliasAnalysis &AA) {
+  if (UnknownInsts.empty())
+    addRef();
   UnknownInsts.push_back(I);
 
   if (!I->mayWriteToMemory()) {
@@ -218,13 +225,14 @@ AliasSet *AliasSetTracker::findAliasSetF
                                                   uint64_t Size,
                                                   const MDNode *TBAAInfo) {
   AliasSet *FoundSet = nullptr;
-  for (iterator I = begin(), E = end(); I != E; ++I) {
-    if (I->Forward || !I->aliasesPointer(Ptr, Size, TBAAInfo, AA)) continue;
+  for (iterator I = begin(), E = end(); I != E;) {
+    iterator Cur = I++;
+    if (Cur->Forward || !Cur->aliasesPointer(Ptr, Size, TBAAInfo, AA)) continue;
     
     if (!FoundSet) {      // If this is the first alias set ptr can go into.
-      FoundSet = I;       // Remember it.
+      FoundSet = Cur;     // Remember it.
     } else {              // Otherwise, we must merge the sets.
-      FoundSet->mergeSetIn(*I, *this);     // Merge in contents.
+      FoundSet->mergeSetIn(*Cur, *this);     // Merge in contents.
     }
   }
 
@@ -246,14 +254,14 @@ bool AliasSetTracker::containsPointer(Va
 
 AliasSet *AliasSetTracker::findAliasSetForUnknownInst(Instruction *Inst) {
   AliasSet *FoundSet = nullptr;
-  for (iterator I = begin(), E = end(); I != E; ++I) {
-    if (I->Forward || !I->aliasesUnknownInst(Inst, AA))
+  for (iterator I = begin(), E = end(); I != E;) {
+    iterator Cur = I++;
+    if (Cur->Forward || !Cur->aliasesUnknownInst(Inst, AA))
       continue;
-    
     if (!FoundSet)            // If this is the first alias set ptr can go into.
-      FoundSet = I;           // Remember it.
-    else if (!I->Forward)     // Otherwise, we must merge the sets.
-      FoundSet->mergeSetIn(*I, *this);     // Merge in contents.
+      FoundSet = Cur;         // Remember it.
+    else if (!Cur->Forward)   // Otherwise, we must merge the sets.
+      FoundSet->mergeSetIn(*Cur, *this);     // Merge in contents.
   }
   return FoundSet;
 }
@@ -393,6 +401,8 @@ void AliasSetTracker::add(const AliasSet
 /// tracker.
 void AliasSetTracker::remove(AliasSet &AS) {
   // Drop all call sites.
+  if (!AS.UnknownInsts.empty())
+    AS.dropRef(*this);
   AS.UnknownInsts.clear();
   
   // Clear the alias set.
@@ -489,10 +499,10 @@ void AliasSetTracker::deleteValue(Value 
   if (Instruction *Inst = dyn_cast<Instruction>(PtrVal)) {
     if (Inst->mayReadOrWriteMemory()) {
       // Scan all the alias sets to see if this call site is contained.
-      for (iterator I = begin(), E = end(); I != E; ++I) {
-        if (I->Forward) continue;
-        
-        I->removeUnknownInst(Inst);
+      for (iterator I = begin(), E = end(); I != E;) {
+        iterator Cur = I++;
+        if (!Cur->Forward)
+          Cur->removeUnknownInst(*this, Inst);
       }
     }
   }

Modified: vendor/llvm/dist/lib/Analysis/BlockFrequencyInfoImpl.cpp
==============================================================================
--- vendor/llvm/dist/lib/Analysis/BlockFrequencyInfoImpl.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Analysis/BlockFrequencyInfoImpl.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -14,7 +14,7 @@
 #include "llvm/Analysis/BlockFrequencyInfoImpl.h"
 #include "llvm/ADT/SCCIterator.h"
 #include "llvm/Support/raw_ostream.h"
-#include <deque>
+#include <numeric>
 
 using namespace llvm;
 using namespace llvm::bfi_detail;
@@ -123,8 +123,12 @@ static void combineWeight(Weight &W, con
   }
   assert(W.Type == OtherW.Type);
   assert(W.TargetNode == OtherW.TargetNode);
-  assert(W.Amount < W.Amount + OtherW.Amount && "Unexpected overflow");
-  W.Amount += OtherW.Amount;
+  assert(OtherW.Amount && "Expected non-zero weight");
+  if (W.Amount > W.Amount + OtherW.Amount)
+    // Saturate on overflow.
+    W.Amount = UINT64_MAX;
+  else
+    W.Amount += OtherW.Amount;
 }
 static void combineWeightsBySorting(WeightList &Weights) {
   // Sort so edges to the same node are adjacent.
@@ -207,11 +211,19 @@ void Distribution::normalize() {
     Shift = 33 - countLeadingZeros(Total);
 
   // Early exit if nothing needs to be scaled.
-  if (!Shift)
+  if (!Shift) {
+    // If we didn't overflow then combineWeights() shouldn't have changed the
+    // sum of the weights, but let's double-check.
+    assert(Total == std::accumulate(Weights.begin(), Weights.end(), UINT64_C(0),
+                                    [](uint64_t Sum, const Weight &W) {
+                      return Sum + W.Amount;
+                    }) &&
+           "Expected total to be correct");
     return;
+  }
 
   // Recompute the total through accumulation (rather than shifting it) so that
-  // it's accurate after shifting.
+  // it's accurate after shifting and any changes combineWeights() made above.
   Total = 0;
 
   // Sum the weights to each node and shift right if necessary.

Modified: vendor/llvm/dist/lib/Analysis/ValueTracking.cpp
==============================================================================
--- vendor/llvm/dist/lib/Analysis/ValueTracking.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Analysis/ValueTracking.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -1987,23 +1987,31 @@ bool llvm::isSafeToSpeculativelyExecute(
   default:
     return true;
   case Instruction::UDiv:
-  case Instruction::URem:
-    // x / y is undefined if y == 0, but calculations like x / 3 are safe.
-    return isKnownNonZero(Inst->getOperand(1), TD);
+  case Instruction::URem: {
+    // x / y is undefined if y == 0.
+    const APInt *V;
+    if (match(Inst->getOperand(1), m_APInt(V)))
+      return *V != 0;
+    return false;
+  }
   case Instruction::SDiv:
   case Instruction::SRem: {
-    Value *Op = Inst->getOperand(1);
-    // x / y is undefined if y == 0
-    if (!isKnownNonZero(Op, TD))
-      return false;
-    // x / y might be undefined if y == -1
-    unsigned BitWidth = getBitWidth(Op->getType(), TD);
-    if (BitWidth == 0)
-      return false;
-    APInt KnownZero(BitWidth, 0);
-    APInt KnownOne(BitWidth, 0);
-    computeKnownBits(Op, KnownZero, KnownOne, TD);
-    return !!KnownZero;
+    // x / y is undefined if y == 0 or x == INT_MIN and y == -1
+    const APInt *X, *Y;
+    if (match(Inst->getOperand(1), m_APInt(Y))) {
+      if (*Y != 0) {
+        if (*Y == -1) {
+          // The numerator can't be MinSignedValue if the denominator is -1.
+          if (match(Inst->getOperand(0), m_APInt(X)))
+            return !Y->isMinSignedValue();
+          // The numerator *might* be MinSignedValue.
+          return false;
+        }
+        // The denominator is not 0 or -1, it's safe to proceed.
+        return true;
+      }
+    }
+    return false;
   }
   case Instruction::Load: {
     const LoadInst *LI = cast<LoadInst>(Inst);

Modified: vendor/llvm/dist/lib/MC/MCObjectFileInfo.cpp
==============================================================================
--- vendor/llvm/dist/lib/MC/MCObjectFileInfo.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/MC/MCObjectFileInfo.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -340,6 +340,8 @@ void MCObjectFileInfo::InitELFMCObjectFi
     break;
   case Triple::mips:
   case Triple::mipsel:
+  case Triple::mips64:
+  case Triple::mips64el:
     // MIPS uses indirect pointer to refer personality functions, so that the
     // eh_frame section can be read-only.  DW.ref.personality will be generated
     // for relocation.

Modified: vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -566,11 +566,59 @@ void ARMFrameLowering::emitPrologue(Mach
     AFI->setShouldRestoreSPFromFP(true);
 }
 
+// Resolve TCReturn pseudo-instruction
+void ARMFrameLowering::fixTCReturn(MachineFunction &MF,
+                                   MachineBasicBlock &MBB) const {
+  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+  assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
+  unsigned RetOpcode = MBBI->getOpcode();
+  DebugLoc dl = MBBI->getDebugLoc();
+  const ARMBaseInstrInfo &TII =
+      *MF.getTarget().getSubtarget<ARMSubtarget>().getInstrInfo();
+
+  if (!(RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri))
+    return;
+
+  // Tail call return: adjust the stack pointer and jump to callee.
+  MBBI = MBB.getLastNonDebugInstr();
+  MachineOperand &JumpTarget = MBBI->getOperand(0);
+
+  // Jump to label or value in register.
+  if (RetOpcode == ARM::TCRETURNdi) {
+    unsigned TCOpcode = STI.isThumb() ?
+             (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
+             ARM::TAILJMPd;
+    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
+    if (JumpTarget.isGlobal())
+      MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
+                           JumpTarget.getTargetFlags());
+    else {
+      assert(JumpTarget.isSymbol());
+      MIB.addExternalSymbol(JumpTarget.getSymbolName(),
+                            JumpTarget.getTargetFlags());
+    }
+
+    // Add the default predicate in Thumb mode.
+    if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
+  } else if (RetOpcode == ARM::TCRETURNri) {
+    BuildMI(MBB, MBBI, dl,
+            TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
+      addReg(JumpTarget.getReg(), RegState::Kill);
+  }
+
+  MachineInstr *NewMI = std::prev(MBBI);
+  for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
+    NewMI->addOperand(MBBI->getOperand(i));
+
+  // Delete the pseudo instruction TCRETURN.
+  MBB.erase(MBBI);
+  MBBI = NewMI;
+}
+
 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
                                     MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
   assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
-  unsigned RetOpcode = MBBI->getOpcode();
   DebugLoc dl = MBBI->getDebugLoc();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
@@ -588,8 +636,10 @@ void ARMFrameLowering::emitEpilogue(Mach
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
-  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
+  if (MF.getFunction()->getCallingConv() == CallingConv::GHC) {
+    fixTCReturn(MF, MBB);
     return;
+  }
 
   if (!AFI->hasStackFrame()) {
     if (NumBytes - ArgRegsSaveSize != 0)
@@ -661,42 +711,7 @@ void ARMFrameLowering::emitEpilogue(Mach
     if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
   }
 
-  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
-    // Tail call return: adjust the stack pointer and jump to callee.
-    MBBI = MBB.getLastNonDebugInstr();
-    MachineOperand &JumpTarget = MBBI->getOperand(0);
-
-    // Jump to label or value in register.
-    if (RetOpcode == ARM::TCRETURNdi) {
-      unsigned TCOpcode = STI.isThumb() ?
-               (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
-               ARM::TAILJMPd;
-      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
-      if (JumpTarget.isGlobal())
-        MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
-                             JumpTarget.getTargetFlags());
-      else {
-        assert(JumpTarget.isSymbol());
-        MIB.addExternalSymbol(JumpTarget.getSymbolName(),
-                              JumpTarget.getTargetFlags());
-      }
-
-      // Add the default predicate in Thumb mode.
-      if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
-    } else if (RetOpcode == ARM::TCRETURNri) {
-      BuildMI(MBB, MBBI, dl,
-              TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
-        addReg(JumpTarget.getReg(), RegState::Kill);
-    }
-
-    MachineInstr *NewMI = std::prev(MBBI);
-    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
-      NewMI->addOperand(MBBI->getOperand(i));
-
-    // Delete the pseudo instruction TCRETURN.
-    MBB.erase(MBBI);
-    MBBI = NewMI;
-  }
+  fixTCReturn(MF, MBB);
 
   if (ArgRegsSaveSize)
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);

Modified: vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.h
==============================================================================
--- vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.h	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.h	Thu Jan 15 22:30:16 2015	(r277220)
@@ -31,6 +31,8 @@ public:
   void emitPrologue(MachineFunction &MF) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
+  void fixTCReturn(MachineFunction &MF, MachineBasicBlock &MBB) const;
+
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,

Modified: vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -1521,7 +1521,7 @@ ARMTargetLowering::LowerCall(TargetLower
       // True if this byval aggregate will be split between registers
       // and memory.
       unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
-      unsigned CurByValIdx = CCInfo.getInRegsParamsProceed();
+      unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
 
       if (CurByValIdx < ByValArgsCount) {
 
@@ -2962,7 +2962,7 @@ ARMTargetLowering::LowerFormalArguments(
         if (Flags.isByVal()) {
           unsigned ExtraArgRegsSize;
           unsigned ExtraArgRegsSaveSize;
-          computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProceed(),
+          computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProcessed(),
                          Flags.getByValSize(),
                          ExtraArgRegsSize, ExtraArgRegsSaveSize);
 
@@ -3086,7 +3086,7 @@ ARMTargetLowering::LowerFormalArguments(
           // Since they could be overwritten by lowering of arguments in case of
           // a tail call.
           if (Flags.isByVal()) {
-            unsigned CurByValIndex = CCInfo.getInRegsParamsProceed();
+            unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
 
             ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
             int FrameIndex = StoreByValRegs(

Modified: vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -200,14 +200,14 @@ class MipsAsmParser : public MCTargetAsm
   // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
   bool validateMSAIndex(int Val, int RegKind);
 
-  void setFeatureBits(unsigned Feature, StringRef FeatureString) {
+  void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
     if (!(STI.getFeatureBits() & Feature)) {
       setAvailableFeatures(
           ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
     }
   }
 
-  void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
+  void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
     if (STI.getFeatureBits() & Feature) {
       setAvailableFeatures(
           ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));

Modified: vendor/llvm/dist/lib/Target/Mips/CMakeLists.txt
==============================================================================
--- vendor/llvm/dist/lib/Target/Mips/CMakeLists.txt	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Target/Mips/CMakeLists.txt	Thu Jan 15 22:30:16 2015	(r277220)
@@ -22,8 +22,10 @@ add_llvm_target(MipsCodeGen
   Mips16ISelDAGToDAG.cpp
   Mips16ISelLowering.cpp
   Mips16RegisterInfo.cpp
+  MipsABIInfo.cpp
   MipsAnalyzeImmediate.cpp
   MipsAsmPrinter.cpp
+  MipsCCState.cpp
   MipsCodeEmitter.cpp
   MipsConstantIslandPass.cpp
   MipsDelaySlotFiller.cpp

Modified: vendor/llvm/dist/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/Mips/Disassembler/MipsDisassembler.cpp	Thu Jan 15 22:17:11 2015	(r277219)
+++ vendor/llvm/dist/lib/Target/Mips/Disassembler/MipsDisassembler.cpp	Thu Jan 15 22:30:16 2015	(r277220)
@@ -250,6 +250,11 @@ static DecodeStatus DecodeMem(MCInst &In
                               uint64_t Address,
                               const void *Decoder);
 
+static DecodeStatus DecodeCacheOp(MCInst &Inst,
+                              unsigned Insn,
+                              uint64_t Address,
+                              const void *Decoder);
+
 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder);
 
@@ -267,6 +272,14 @@ static DecodeStatus DecodeFMem(MCInst &I
                                uint64_t Address,
                                const void *Decoder);
 
+static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
+                               uint64_t Address,
+                               const void *Decoder);
+
+static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
+                               uint64_t Address,
+                               const void *Decoder);
+
 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,
@@ -451,7 +464,7 @@ static DecodeStatus DecodeAddiGroupBranc
 
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
   bool HasRs = false;
 
   if (Rs >= Rt) {
@@ -490,7 +503,7 @@ static DecodeStatus DecodeDaddiGroupBran
 
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
   bool HasRs = false;
 
   if (Rs >= Rt) {
@@ -530,7 +543,7 @@ static DecodeStatus DecodeBlezlGroupBran
 
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
   bool HasRs = false;
 
   if (Rt == 0)
@@ -575,7 +588,7 @@ static DecodeStatus DecodeBgtzlGroupBran
 
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 
   if (Rt == 0)
     return MCDisassembler::Fail;
@@ -617,7 +630,7 @@ static DecodeStatus DecodeBgtzGroupBranc
 
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
   bool HasRs = false;
   bool HasRt = false;
 
@@ -666,7 +679,7 @@ static DecodeStatus DecodeBlezGroupBranc
 
   InsnType Rs = fieldFromInstruction(insn, 21, 5);
   InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
   bool HasRs = false;
 
   if (Rt == 0)
@@ -964,6 +977,23 @@ static DecodeStatus DecodeMem(MCInst &In
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeCacheOp(MCInst &Inst,
+                              unsigned Insn,
+                              uint64_t Address,
+                              const void *Decoder) {
+  int Offset = SignExtend32<16>(Insn & 0xffff);
+  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  Inst.addOperand(MCOperand::CreateReg(Base));
+  Inst.addOperand(MCOperand::CreateImm(Offset));
+  Inst.addOperand(MCOperand::CreateImm(Hint));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder) {
   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
@@ -995,15 +1025,15 @@ static DecodeStatus DecodeMSA128Mem(MCIn
     break;
   case Mips::LD_H:
   case Mips::ST_H:
-    Inst.addOperand(MCOperand::CreateImm(Offset << 1));
+    Inst.addOperand(MCOperand::CreateImm(Offset * 2));
     break;
   case Mips::LD_W:
   case Mips::ST_W:
-    Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+    Inst.addOperand(MCOperand::CreateImm(Offset * 4));
     break;
   case Mips::LD_D:
   case Mips::ST_D:
-    Inst.addOperand(MCOperand::CreateImm(Offset << 3));
+    Inst.addOperand(MCOperand::CreateImm(Offset * 8));
     break;
   }
 
@@ -1067,6 +1097,42 @@ static DecodeStatus DecodeFMem(MCInst &I
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeFMem2(MCInst &Inst,
+                               unsigned Insn,
+                               uint64_t Address,
+                               const void *Decoder) {
+  int Offset = SignExtend32<16>(Insn & 0xffff);
+  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  Inst.addOperand(MCOperand::CreateReg(Base));
+  Inst.addOperand(MCOperand::CreateImm(Offset));
+
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFMem3(MCInst &Inst,
+                               unsigned Insn,
+                               uint64_t Address,
+                               const void *Decoder) {
+  int Offset = SignExtend32<16>(Insn & 0xffff);
+  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+  Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  Inst.addOperand(MCOperand::CreateReg(Base));
+  Inst.addOperand(MCOperand::CreateImm(Offset));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,
@@ -1225,7 +1291,7 @@ static DecodeStatus DecodeBranchTarget(M
                                        unsigned Offset,
                                        uint64_t Address,
                                        const void *Decoder) {
-  int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
+  int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
   return MCDisassembler::Success;
 }
@@ -1244,7 +1310,7 @@ static DecodeStatus DecodeBranchTarget21
                                          unsigned Offset,
                                          uint64_t Address,
                                          const void *Decoder) {
-  int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
+  int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
 
   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
   return MCDisassembler::Success;
@@ -1254,7 +1320,7 @@ static DecodeStatus DecodeBranchTarget26
                                          unsigned Offset,
                                          uint64_t Address,
                                          const void *Decoder) {
-  int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
+  int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
 
   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
   return MCDisassembler::Success;
@@ -1264,7 +1330,7 @@ static DecodeStatus DecodeBranchTargetMM
                                          unsigned Offset,
                                          uint64_t Address,

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***


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