svn commit: r292681 - head/sys/mips/mips

[Adrian Chadd]

Author: adrian
Date: Thu Dec 24 04:37:19 2015
New Revision: 292681
URL: https://svnweb.freebsd.org/changeset/base/292681

Log:
  Add missing \n.
  
  Otherwise you end up with:
  
  Cache info:
    picache_stride    = 4096
    picache_loopcount = 16
    pdcache_stride    = 4096
    pdcache_loopcount = 8
  cpu0: MIPS Technologies processor v80.150
    MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
    L1 i-cache: 4 ways of 512 sets, 32 bytes per line
    L1 d-cache: 4 ways of 256 sets, 32 bytes per line
    L2 cache: disabled  Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
    Config2=0x80000000
    Config3=0x2420
  
  Tested:
  
  * MT7620 SoC

Modified:
  head/sys/mips/mips/cpu.c

Modified: head/sys/mips/mips/cpu.c
==============================================================================
--- head/sys/mips/mips/cpu.c	Thu Dec 24 04:30:15 2015	(r292680)
+++ head/sys/mips/mips/cpu.c	Thu Dec 24 04:37:19 2015	(r292681)
@@ -351,7 +351,7 @@ cpu_identify(void)
 
 	printf("  L2 cache: ");
 	if (cpuinfo.l2.dc_linesize == 0) {
-		printf("disabled");
+		printf("disabled\n");
 	} else {
 		printf("%d ways of %d sets, %d bytes per line, "
 		    "%d KiB total size\n",