svn commit: r266083 - in head/sys/arm: arm include

[Michael Tuexen]

On 15 Jun 2014, at 17:13, Mark R V Murray <markm at FreeBSD.org> wrote:

> 
> On 30 May 2014, at 09:42, Michael Tuexen <tuexen at fh-muenster.de> wrote:
> 
>> On 29 May 2014, at 21:21, Mark R V Murray <markm at FreeBSD.org> wrote:
>> 
>>> 
>>> On 29 May 2014, at 19:27, Michael Tuexen <tuexen at fh-muenster.de> wrote:
>>> 
>>>> On 29 May 2014, at 20:15, Mark R V Murray <markm at FreeBSD.org> wrote:
>>>> 
>>>>> 
>>>>> On 29 May 2014, at 19:13, Michael Tuexen <tuexen at fh-muenster.de> wrote:
>>>>> 
>>>>>>> I can make it work on RPI, but trying to find what else it will/won’t work on is more problematic.
>>>>>> Wouldn't it require to use different registers on the RPI? This would mean you
>>>>>> would need more #ifdefs…
>>>>> 
>>>>> Thats the problem; too many #ifdefs.
>>>> So you could just keep the code for now, but reduce the #ifdefs to the ones you
>>>> know that work. Later on, you can replace it by the driver stuff…
>>> 
>>> That’s what I was thinking, yes.
>> Great. Let me know if you need testing support on the RPI…
> 
> I’ve come to the conclusion that my RPI-B is hosed. It doesn’t even boot Raspian properly. Sorry about how long this has taken.
> 
> Please could someone with a working RPI please check that the following patch works (may need to apply by hand due to cut/paste).
Hi Mark,

your patch for accessing the value is correct. However, the initialisation code also
needs to be adopted to the platform. So in addition to your patch, you also need:

Index: arm/cpufunc.c
===================================================================
--- arm/cpufunc.c	(revision 267519)
+++ arm/cpufunc.c	(working copy)
@@ -1415,6 +1415,12 @@
 			:
 			: "r"(0x00000001));
 #endif
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+	/* Set PMCR[2,0] to enable counters and reset CCNT */
+	__asm volatile ("mcr	p15, 0, %0, c15, c12, 0\n\t"
+			:
+			: "r"(0x00000005));
+#else
         /* Set up the PMCCNTR register as a cyclecounter:
 	 * Set PMINTENCLR to 0xFFFFFFFF to block interrupts
 	 * Set PMCR[2,0] to enable counters and reset CCNT
@@ -1426,6 +1432,7 @@
 			: "r"(0xFFFFFFFF),
 			  "r"(0x00000005),
 			  "r"(0x80000000));
+#endif
 }
 #endif
 
With both patches, the RPI boots up fine with r267519

Is there an easy test to see if the code actually works as expected and not that it just
allows the system to boot?
Regarding the 32-bit limitation: Do we want to increment the register only every
64 clock cycle?

Best regards
Michael
> 
> Thanks, with repeated apologies.
> 
> M
> -- 
> Mark R V Murray
> 
> --- include/cpu.h	(revision 267507)
> +++ include/cpu.h	(working copy)
> @@ -25,7 +25,16 @@
> 	 * Read PMCCNTR. Curses! Its only 32 bits.
> 	 * TODO: Fix this by catching overflow with interrupt?
> 	 */
> +/* The ARMv6 vs ARMv7 divide is going to need a better way of
> + * distinguishing between them.
> + */
> +#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
> +	/* ARMv6 - Earlier model SCCs */
> +	__asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
> +#else
> +	/* ARMv7 - Later model SCCs */
> 	__asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
> +#endif
> 	ccnt64 = (uint64_t)ccnt;
> 	return (ccnt64);
> #else /* No performance counters, so use binuptime(9). This is slooooow */
> 
>