svn commit: r261322 - head/sys/arm/at91
Warner Losh
imp at FreeBSD.org
Fri Jan 31 15:38:07 UTC 2014
Author: imp
Date: Fri Jan 31 15:38:05 2014
New Revision: 261322
URL: http://svnweb.freebsd.org/changeset/base/261322
Log:
Switch to using PAs rather than VAs for the addresses we map for
devices. This is a nop, except for what's reported by atmelbus for the
resources.
It would be nice if we could dymanically allocated these things, but
the pmap_mapdev panics if we don't keep the static mappings, so we
still need to play the carefully allocate VA space between all
supported SoC game.
User's with their own devices may need to make adjustments.
Modified:
head/sys/arm/at91/at91.c
head/sys/arm/at91/at91_machdep.c
head/sys/arm/at91/at91rm92reg.h
head/sys/arm/at91/at91sam9g20reg.h
head/sys/arm/at91/at91sam9g45reg.h
Modified: head/sys/arm/at91/at91.c
==============================================================================
--- head/sys/arm/at91/at91.c Fri Jan 31 14:29:34 2014 (r261321)
+++ head/sys/arm/at91/at91.c Fri Jan 31 15:38:05 2014 (r261322)
@@ -260,7 +260,6 @@ static int
at91_attach(device_t dev)
{
struct at91_softc *sc = device_get_softc(dev);
- const struct arm_devmap_entry *pdevmap;
int i;
arm_post_filter = at91_eoi;
@@ -281,11 +280,15 @@ at91_attach(device_t dev)
sc->sc_mem_rman.rm_descr = "AT91 Memory";
if (rman_init(&sc->sc_mem_rman) != 0)
panic("at91_attach: failed to set up memory rman");
- for (pdevmap = at91_devmap; pdevmap->pd_va != 0; pdevmap++) {
- if (rman_manage_region(&sc->sc_mem_rman, pdevmap->pd_va,
- pdevmap->pd_va + pdevmap->pd_size - 1) != 0)
- panic("at91_attach: failed to set up memory rman");
- }
+ /*
+ * Manage the physical space, defined as being everything that isn't
+ * DRAM.
+ */
+ if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0)
+ panic("at91_attach: failed to set up memory rman");
+ if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20),
+ 0xfffffffful) != 0)
+ panic("at91_attach: failed to set up memory rman");
/*
* Setup the interrupt table.
@@ -330,6 +333,7 @@ at91_alloc_resource(device_t dev, device
struct resource_list_entry *rle;
struct at91_ivar *ivar = device_get_ivars(child);
struct resource_list *rl = &ivar->resources;
+ bus_space_handle_t bsh;
if (device_get_parent(child) != dev)
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
@@ -355,8 +359,10 @@ at91_alloc_resource(device_t dev, device
rle->res = rman_reserve_resource(&sc->sc_mem_rman,
start, end, count, flags, child);
if (rle->res != NULL) {
+ bus_space_map(&at91_bs_tag, start,
+ rman_get_size(rle->res), 0, &bsh);
rman_set_bustag(rle->res, &at91_bs_tag);
- rman_set_bushandle(rle->res, start);
+ rman_set_bushandle(rle->res, bsh);
}
break;
}
@@ -538,8 +544,14 @@ at91_add_child(device_t dev, int prio, c
bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
if (irq2 != 0)
bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
- if (addr != 0 && addr < AT91_BASE)
- addr += AT91_BASE;
+ /*
+ * Special case for on-board devices. These have their address
+ * defined relative to AT91_PA_BASE in all the register files we
+ * have. We could change this, but that's a lot of effort which
+ * will be obsoleted when FDT arrives.
+ */
+ if (addr != 0 && addr < 0x10000000 && addr >= 0x0f000000)
+ addr += AT91_PA_BASE;
if (addr != 0)
bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
}
Modified: head/sys/arm/at91/at91_machdep.c
==============================================================================
--- head/sys/arm/at91/at91_machdep.c Fri Jan 31 14:29:34 2014 (r261321)
+++ head/sys/arm/at91/at91_machdep.c Fri Jan 31 15:38:05 2014 (r261322)
@@ -146,6 +146,7 @@ const struct arm_devmap_entry at91_devma
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
+ /* There's a notion that we should do the rest of these lazily. */
/*
* We can't just map the OHCI registers VA == PA, because
* AT91xx_xxx_BASE belongs to the userland address space.
@@ -163,16 +164,16 @@ const struct arm_devmap_entry at91_devma
* on this chip select for a VA/PA mapping.
*/
/* Internal Memory 1MB */
+ AT91RM92_OHCI_VA_BASE,
AT91RM92_OHCI_BASE,
- AT91RM92_OHCI_PA_BASE,
0x00100000,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
/* CompactFlash controller. Portion of EBI CS4 1MB */
+ AT91RM92_CF_VA_BASE,
AT91RM92_CF_BASE,
- AT91RM92_CF_PA_BASE,
0x00100000,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
@@ -183,16 +184,16 @@ const struct arm_devmap_entry at91_devma
*/
{
/* Internal Memory 1MB */
+ AT91SAM9G20_OHCI_VA_BASE,
AT91SAM9G20_OHCI_BASE,
- AT91SAM9G20_OHCI_PA_BASE,
0x00100000,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
/* EBI CS3 256MB */
+ AT91SAM9G20_NAND_VA_BASE,
AT91SAM9G20_NAND_BASE,
- AT91SAM9G20_NAND_PA_BASE,
AT91SAM9G20_NAND_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
@@ -202,8 +203,8 @@ const struct arm_devmap_entry at91_devma
*/
{
/* Internal Memory 1MB */
+ AT91SAM9G45_OHCI_VA_BASE,
AT91SAM9G45_OHCI_BASE,
- AT91SAM9G45_OHCI_PA_BASE,
0x00100000,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
Modified: head/sys/arm/at91/at91rm92reg.h
==============================================================================
--- head/sys/arm/at91/at91rm92reg.h Fri Jan 31 14:29:34 2014 (r261321)
+++ head/sys/arm/at91/at91rm92reg.h Fri Jan 31 15:38:05 2014 (r261322)
@@ -255,12 +255,12 @@
* other * soc's so phyical and vm address
* mapping are unique. XXX
*/
-#define AT91RM92_OHCI_BASE 0xdfe00000
-#define AT91RM92_OHCI_PA_BASE 0x00300000
+#define AT91RM92_OHCI_VA_BASE 0xdfe00000
+#define AT91RM92_OHCI_BASE 0x00300000
#define AT91RM92_OHCI_SIZE 0x00100000
-#define AT91RM92_CF_BASE 0xdfd00000
-#define AT91RM92_CF_PA_BASE 0x51400000
+#define AT91RM92_CF_VA_BASE 0xdfd00000
+#define AT91RM92_CF_BASE 0x51400000
#define AT91RM92_CF_SIZE 0x00100000
/* SDRAMC */
Modified: head/sys/arm/at91/at91sam9g20reg.h
==============================================================================
--- head/sys/arm/at91/at91sam9g20reg.h Fri Jan 31 14:29:34 2014 (r261321)
+++ head/sys/arm/at91/at91sam9g20reg.h Fri Jan 31 15:38:05 2014 (r261322)
@@ -252,14 +252,13 @@
* other * soc's so phyical and vm address
* mapping are unique. XXX
*/
-#define AT91SAM9G20_OHCI_BASE 0xdfc00000
-#define AT91SAM9G20_OHCI_PA_BASE 0x00500000
-#define AT91SAM9G20_OHCI_SIZE 0x00100000
-
-#define AT91SAM9G20_NAND_BASE 0xe0000000
-#define AT91SAM9G20_NAND_PA_BASE 0x40000000
-#define AT91SAM9G20_NAND_SIZE 0x10000000
+#define AT91SAM9G20_OHCI_VA_BASE 0xdfc00000
+#define AT91SAM9G20_OHCI_BASE 0x00500000
+#define AT91SAM9G20_OHCI_SIZE 0x00100000
+#define AT91SAM9G20_NAND_VA_BASE 0xe0000000
+#define AT91SAM9G20_NAND_BASE 0x40000000
+#define AT91SAM9G20_NAND_SIZE 0x10000000
/* SDRAMC */
#define AT91SAM9G20_SDRAMC_BASE 0xfffea00
Modified: head/sys/arm/at91/at91sam9g45reg.h
==============================================================================
--- head/sys/arm/at91/at91sam9g45reg.h Fri Jan 31 14:29:34 2014 (r261321)
+++ head/sys/arm/at91/at91sam9g45reg.h Fri Jan 31 15:38:05 2014 (r261322)
@@ -243,13 +243,13 @@
* other * soc's so phyical and vm address
* mapping are unique. XXX
*/
-#define AT91SAM9G45_OHCI_BASE 0xdfb00000
-#define AT91SAM9G45_OHCI_PA_BASE 0x00700000
-#define AT91SAM9G45_OHCI_SIZE 0x00100000
+#define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000
+#define AT91SAM9G45_OHCI_BASE 0x00700000
+#define AT91SAM9G45_OHCI_SIZE 0x00100000
-#define AT91SAM9G45_NAND_BASE 0xe0000000
-#define AT91SAM9G45_NAND_PA_BASE 0x40000000
-#define AT91SAM9G45_NAND_SIZE 0x10000000
+#define AT91SAM9G45_NAND_VA_BASE 0xe0000000
+#define AT91SAM9G45_NAND_BASE 0x40000000
+#define AT91SAM9G45_NAND_SIZE 0x10000000
/* DDRSDRC */
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