svn commit: r260357 - in stable/7: share/man/man4 sys/amd64/conf sys/conf sys/dev/bxe sys/i386/conf sys/modules/bxe
Eric Davis
edavis at FreeBSD.org
Sun Jan 5 23:13:21 UTC 2014
Author: edavis
Date: Sun Jan 5 23:13:18 2014
New Revision: 260357
URL: http://svnweb.freebsd.org/changeset/base/260357
Log:
MFC Broadcom 10Gb bxe driver
Merged r255736, r255861, r256299, r256341, r258187, r259928, r260113
Approved by: davidch (mentor)
Added:
stable/7/share/man/man4/bxe.4 (contents, props changed)
stable/7/sys/dev/bxe/
stable/7/sys/dev/bxe/57710_init_values.c (contents, props changed)
stable/7/sys/dev/bxe/57710_int_offsets.h (contents, props changed)
stable/7/sys/dev/bxe/57711_init_values.c (contents, props changed)
stable/7/sys/dev/bxe/57711_int_offsets.h (contents, props changed)
stable/7/sys/dev/bxe/57712_init_values.c (contents, props changed)
stable/7/sys/dev/bxe/57712_int_offsets.h (contents, props changed)
stable/7/sys/dev/bxe/bxe.c (contents, props changed)
stable/7/sys/dev/bxe/bxe.h (contents, props changed)
stable/7/sys/dev/bxe/bxe_dcb.h (contents, props changed)
stable/7/sys/dev/bxe/bxe_debug.c (contents, props changed)
stable/7/sys/dev/bxe/bxe_elink.c (contents, props changed)
stable/7/sys/dev/bxe/bxe_elink.h (contents, props changed)
stable/7/sys/dev/bxe/bxe_stats.c (contents, props changed)
stable/7/sys/dev/bxe/bxe_stats.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_fw_defs.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_hsi.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_init.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_init_ops.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_mfw_req.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_reg.h (contents, props changed)
stable/7/sys/dev/bxe/ecore_sp.c (contents, props changed)
stable/7/sys/dev/bxe/ecore_sp.h (contents, props changed)
stable/7/sys/modules/bxe/
stable/7/sys/modules/bxe/Makefile (contents, props changed)
Modified:
stable/7/share/man/man4/altq.4
stable/7/share/man/man4/vlan.4
stable/7/sys/amd64/conf/GENERIC
stable/7/sys/amd64/conf/NOTES
stable/7/sys/conf/NOTES
stable/7/sys/conf/files
stable/7/sys/conf/files.amd64
stable/7/sys/conf/files.i386
stable/7/sys/i386/conf/GENERIC
stable/7/sys/i386/conf/NOTES
Directory Properties:
stable/7/share/ (props changed)
stable/7/share/man/ (props changed)
stable/7/share/man/man4/ (props changed)
stable/7/sys/ (props changed)
Modified: stable/7/share/man/man4/altq.4
==============================================================================
--- stable/7/share/man/man4/altq.4 Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/share/man/man4/altq.4 Sun Jan 5 23:13:18 2014 (r260357)
@@ -127,6 +127,7 @@ They have been applied to the following
.Xr bce 4 ,
.Xr bfe 4 ,
.Xr bge 4 ,
+.Xr bxe 4 ,
.Xr cas 4 ,
.Xr dc 4 ,
.Xr de 4 ,
Added: stable/7/share/man/man4/bxe.4
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/7/share/man/man4/bxe.4 Sun Jan 5 23:13:18 2014 (r260357)
@@ -0,0 +1,341 @@
+.\" Copyright (c) 2013 Broadcom Corporation. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\" 3. Neither the name of Broadcom Corporation nor the name of its contributors
+.\" may be used to endorse or promote products derived from this software
+.\" without specific prior written consent.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd April 29, 2012
+.Dt BXE 4
+.Os
+.Sh NAME
+.Nm bxe
+.Nd Broadcom NetXtreme II Ethernet 10Gb PCIe adapter driver
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following lines in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device bxe"
+.Ed
+.Pp
+Alternatively, to load the driver as a module at boot time, place the
+following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+if_bxe_load="YES"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for PCIe 10Gb Ethernet adapters based on the Broadcom
+NetXtreme II family of 10Gb chips.
+The driver supports Jumbo Frames, VLAN
+tagging, checksum offload (IPv4, TCP, UDP, IPv6-TCP, IPv6-UDP), MSI-X
+interrupts, TCP Segmentation Offload (TSO), Large Receive Offload (LRO), and
+Receive Side Scaling (RSS).
+.Sh HARDWARE
+The
+.Nm
+driver provides support for various NICs based on the Broadcom NetXtreme II
+family of 10Gb Ethernet controller chips, including the following:
+.Pp
+.Bl -bullet -compact
+.It
+Broadcom NetXtreme II BCM57710 10Gb
+.It
+Broadcom NetXtreme II BCM57711 10Gb
+.It
+Broadcom NetXtreme II BCM57711E 10Gb
+.It
+Broadcom NetXtreme II BCM57712 10Gb
+.It
+Broadcom NetXtreme II BCM57712-MF 10Gb
+.It
+Broadcom NetXtreme II BCM57800 10Gb
+.It
+Broadcom NetXtreme II BCM57800-MF 10Gb
+.It
+Broadcom NetXtreme II BCM57810 10Gb
+.It
+Broadcom NetXtreme II BCM57810-MF 10Gb
+.It
+Broadcom NetXtreme II BCM57840 10Gb / 20Gb
+.It
+Broadcom NetXtreme II BCM57840-MF 10Gb
+.El
+.Sh CONFIGURATION
+There a number of configuration parameters that can be set to tweak the
+driver's behavior.
+These parameters can be set via the
+.Xr loader.conf 5
+file to take affect during the next system boot.
+The following parameters affect
+ALL instances of the driver.
+.Bl -tag -width indent
+.It Va hw.bxe.debug
+DEFAULT = 0
+.br
+Sets the default logging level of the driver.
+See the Diagnostics and Debugging
+section below for more details.
+.It Va hw.bxe.interrupt_mode
+DEFAULT = 2
+.br
+Sets the default interrupt mode: 0=IRQ, 1=MSI, 2=MSIX.
+If set to MSIX and
+allocation fails, the driver will roll back and attempt MSI allocation.
+If MSI
+allocation fails, the driver will roll back and attempt fixed level IRQ
+allocation.
+If IRQ allocation fails, then the driver load fails.
+With MSI/MSIX,
+the driver attempts to allocate a vector for each queue in addition to one more
+for default processing.
+.It Va hw.bxe.queue_count
+DEFAULT = 4
+.br
+Sets the default number of fast path packet processing queues.
+Note that one
+MSI/MSIX interrupt vector is allocated per-queue.
+.It Va hw.bxe.max_rx_bufs
+DEFAULT = 0
+.br
+Sets the maximum number of receive buffers to allocate per-queue.
+Zero(0) means
+to allocate a receive buffer for every buffer descriptor.
+By default this
+equates to 4080 buffers per-queue which is the maximum value for this config
+parameter.
+.It Va hw.bxe.hc_rx_ticks
+DEFAULT = 25
+.br
+Sets the number of ticks for host interrupt coalescing in the receive path.
+.It Va hw.bxe.hc_tx_ticks
+DEFAULT = 50
+.br
+Sets the number of ticks for host interrupt coalescing in the transmit path.
+.It Va hw.bxe.rx_budget
+DEFAULT = 0xffffffff
+.br
+Sets the maximum number of receive packets to process in an interrupt.
+If the
+budget is reached then the remaining/pending packets will be processed in a
+scheduled taskqueue.
+.It Va hw.bxe.max_aggregation_size
+DEFAULT = 32768
+.br
+Sets the maximum LRO aggregration byte size.
+The higher the value the more
+packets the hardware will aggregate.
+Maximum is 65K.
+.It Va hw.bxe.mrrs
+DEFAULT = -1
+.br
+Sets the PCI MRRS: -1=Auto, 0=128B, 1=256B, 2=512B, 3=1KB
+.It Va hw.bxe.autogreeen
+DEFAULT = 0
+.br
+Set AutoGrEEEN: 0=HW_DEFAULT, 1=FORCE_ON, 2=FORCE_OFF
+.It Va hw.bxe.udp_rss
+DEFAULT = 0
+.br
+Enable/Disable 4-tuple RSS for UDP: 0=DISABLED, 1=ENABLED
+.El
+.Pp
+Special care must be taken when modifying the number of queues and receive
+buffers.
+FreeBSD imposes a limit on the maximum number of
+.Xr mbuf 9
+allocations.
+If buffer allocations fail, the interface initialization will fail
+and the interface will not be usable.
+The driver does not make a best effort
+for buffer allocations.
+It is an all or nothing effort.
+.Pp
+You can tweak the
+.Xr mbuf 9
+allocation limit using
+.Xr sysctl 8
+and view the current usage with
+.Xr netstat 1
+as follows:
+.Bd -literal -offset indent
+# netstat -m
+# sysctl kern.ipc.nmbclusters
+# sysctl kern.ipc.nmbclusters=<#>
+.Ed
+.Pp
+There are additional configuration parameters that can be set on a per-instance
+basis to dynamically override the default configuration.
+The '#' below must be
+replaced with the driver instance / interface unit number:
+.Bl -tag -width indent
+.It Va dev.bxe.#.debug
+DEFAULT = 0
+.br
+Sets the default logging level of the driver instance.
+See
+.Va hw.bxe.debug
+above and
+the Diagnostics and Debugging section below for more details.
+.It Va dev.bxe.#.rx_budget
+DEFAULT = 0xffffffff
+.br
+Sets the maximum number of receive packets to process in an interrupt for the
+driver instance.
+See
+.Va hw.bxe.rx_budget
+above for more details.
+.El
+.Pp
+Additional items can be configured using
+.Xr ifconfig 8 :
+.Bl -tag -width indent
+.It Va MTU - Maximum Transmission Unit
+DEFAULT = 1500
+.br
+RANGE = 46-9184
+.br
+# ifconfig bxe# mtu <n>
+.It Va Promiscuous Mode
+DEFAULT = OFF
+.br
+# ifconfig bxe# [ promisc | -promisc ]
+.It Va Rx/Tx Checksum Offload
+DEFAULT = RX/TX CSUM ON
+.br
+Note that the Rx and Tx settings are not independent.
+.br
+# ifconfig bxe# [ rxcsum | -rxcsum | txcsum | -txcsum ]
+.It Va TSO - TCP Segmentation Offload
+DEFAULT = ON
+.br
+# ifconfig bxe# [ tso | -tso | tso6 | -tso6 ]
+.It Va LRO - TCP Large Receive Offload
+DEFAULT = ON
+.br
+# ifconfig bxe# [ lro | -lro ]
+.El
+.Sh DIAGNOSTICS AND DEBUGGING
+There are many statistics exposed by
+.Nm
+via
+.Xr sysctl 8 .
+.Pp
+To dump the default driver configuration:
+.Bd -literal -offset indent
+# sysctl -a | grep hw.bxe
+.Ed
+.Pp
+To dump every instance's configuration and detailed statistics:
+.Bd -literal -offset indent
+# sysctl -a | grep dev.bxe
+.Ed
+.Pp
+To dump information for a single instance (replace the '#' with the driver
+instance / interface unit number):
+.Bd -literal -offset indent
+# sysctl -a | grep dev.bxe.#
+.Ed
+.Pp
+To dump information for all the queues of a single instance:
+.Bd -literal -offset indent
+# sysctl -a | grep dev.bxe.#.queue
+.Ed
+.Pp
+To dump information for a single queue of a single instance (replace the
+additional '#' with the queue number):
+.Bd -literal -offset indent
+# sysctl -a | grep dev.bxe.#.queue.#
+.Ed
+.Pp
+The
+.Nm
+driver has the ability to dump a ton of debug messages to the system
+log.
+The default level of logging can be set with the
+.Va hw.bxe.debug
+.Xr sysctl 8 .
+Take care with this setting as it can result in too
+many logs being dumped.
+Since this parameter is the default one, it affects
+every instance and will dramatically change the timing in the driver.
+A better
+alternative to aid in debugging is to dynamically change the debug level of a
+specific instance with the
+.Va dev.bxe.#.debug
+.Xr sysctl 8 .
+This allows
+you to turn on/off logging of various debug groups on-the-fly.
+.Pp
+The different debug groups that can be toggled are:
+.Bd -literal -offset indent
+DBG_LOAD 0x00000001 /* load and unload */
+DBG_INTR 0x00000002 /* interrupt handling */
+DBG_SP 0x00000004 /* slowpath handling */
+DBG_STATS 0x00000008 /* stats updates */
+DBG_TX 0x00000010 /* packet transmit */
+DBG_RX 0x00000020 /* packet receive */
+DBG_PHY 0x00000040 /* phy/link handling */
+DBG_IOCTL 0x00000080 /* ioctl handling */
+DBG_MBUF 0x00000100 /* dumping mbuf info */
+DBG_REGS 0x00000200 /* register access */
+DBG_LRO 0x00000400 /* lro processing */
+DBG_ASSERT 0x80000000 /* debug assert */
+DBG_ALL 0xFFFFFFFF /* flying monkeys */
+.Ed
+.Pp
+For example, to debug an issue in the receive path on bxe0:
+.Bd -literal -offset indent
+# sysctl dev.bxe.0.debug=0x22
+.Ed
+.Pp
+When finished turn the logging back off:
+.Bd -literal -offset indent
+# sysctl dev.bxe.0.debug=0
+.Ed
+.Sh SEE ALSO
+.Xr netstat 1 ,
+.Xr altq 4 ,
+.Xr arp 4 ,
+.Xr netintro 4 ,
+.Xr ng_ether 4 ,
+.Xr vlan 4 ,
+.Xr ifconfig 8
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 9.0 .
+.Sh AUTHORS
+The
+.Nm
+driver was written by
+.An Eric Davis Aq edavis at broadcom.com ,
+.An David Christensen Aq davidch at broadcom.com ,
+and
+.An Gary Zambrano Aq zambrano at broadcom.com .
Modified: stable/7/share/man/man4/vlan.4
==============================================================================
--- stable/7/share/man/man4/vlan.4 Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/share/man/man4/vlan.4 Sun Jan 5 23:13:18 2014 (r260357)
@@ -127,6 +127,7 @@ in hardware:
.Xr ale 4 ,
.Xr bce 4 ,
.Xr bge 4 ,
+.Xr bxe 4 ,
.Xr cxgb 4 ,
.Xr em 4 ,
.Xr igb 4 ,
Modified: stable/7/sys/amd64/conf/GENERIC
==============================================================================
--- stable/7/sys/amd64/conf/GENERIC Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/sys/amd64/conf/GENERIC Sun Jan 5 23:13:18 2014 (r260357)
@@ -184,6 +184,7 @@ device ppi # Parallel port interface d
#device puc
# PCI Ethernet NICs.
+device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
device de # DEC/Intel DC21x4x (``Tulip'')
device em # Intel PRO/1000 Gigabit Ethernet Family
device igb # Intel PRO/1000 PCIE Server Gigabit Family
Modified: stable/7/sys/amd64/conf/NOTES
==============================================================================
--- stable/7/sys/amd64/conf/NOTES Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/sys/amd64/conf/NOTES Sun Jan 5 23:13:18 2014 (r260357)
@@ -306,6 +306,8 @@ options DRM_DEBUG # Include debug print
#
# ath: Atheros a/b/g WiFi adapters (requires ath_hal and wlan)
+# bxe: Broadcom NetXtreme II (BCM5771X/BCM578XX) PCIe 10Gb Ethernet
+# adapters.
# ed: Western Digital and SMC 80xx; Novell NE1000 and NE2000; 3Com 3C503
# HP PC Lan+, various PC Card devices
# (requires miibus)
@@ -317,6 +319,7 @@ options DRM_DEBUG # Include debug print
# ural: Ralink Technology RT2500USB IEEE 802.11 wireless adapter
# wpi: Intel 3945ABG Wireless LAN controller
+device bxe # Broadcom NetXtreme II BCM5771X/BCM578XX 10GbE
device ed
options ED_3C503
options ED_HPP
Modified: stable/7/sys/conf/NOTES
==============================================================================
--- stable/7/sys/conf/NOTES Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/sys/conf/NOTES Sun Jan 5 23:13:18 2014 (r260357)
@@ -1773,6 +1773,8 @@ device xmphy # XaQti XMAC II
# BCM570x family of controllers, including the 3Com 3c996-T,
# the Netgear GA302T, the SysKonnect SK-9D21 and SK-9D41, and
# the embedded gigE NICs on Dell PowerEdge 2550 servers.
+# bxe: Broadcom NetXtreme II (BCM5771X/BCM578XX) PCIe 10Gb Ethernet
+# adapters.
# cas: Sun Cassini/Cassini+ and National Semiconductor DP83065 Saturn
# cm: Arcnet SMC COM90c26 / SMC COM90c56
# (and SMC COM90c66 in '56 compatibility mode) adapters.
Modified: stable/7/sys/conf/files
==============================================================================
--- stable/7/sys/conf/files Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/sys/conf/files Sun Jan 5 23:13:18 2014 (r260357)
@@ -669,6 +669,7 @@ dev/buslogic/bt_isa.c optional bt isa
dev/buslogic/bt_mca.c optional bt mca
dev/buslogic/bt_pci.c optional bt pci
dev/cardbus/cardbus.c optional cardbus
+dev/cardbus/cardbus.c optional cardbus
dev/cardbus/cardbus_cis.c optional cardbus
dev/cardbus/cardbus_device.c optional cardbus
dev/cas/if_cas.c optional cas
Modified: stable/7/sys/conf/files.amd64
==============================================================================
--- stable/7/sys/conf/files.amd64 Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/sys/conf/files.amd64 Sun Jan 5 23:13:18 2014 (r260357)
@@ -144,6 +144,14 @@ dev/atkbdc/atkbdc.c optional atkbdc
dev/atkbdc/atkbdc_isa.c optional atkbdc isa
dev/atkbdc/atkbdc_subr.c optional atkbdc
dev/atkbdc/psm.c optional psm atkbdc
+dev/bxe/bxe.c optional bxe pci
+dev/bxe/bxe_stats.c optional bxe pci
+dev/bxe/bxe_debug.c optional bxe pci
+dev/bxe/ecore_sp.c optional bxe pci
+dev/bxe/bxe_elink.c optional bxe pci
+dev/bxe/57710_init_values.c optional bxe pci
+dev/bxe/57711_init_values.c optional bxe pci
+dev/bxe/57712_init_values.c optional bxe pci
dev/coretemp/coretemp.c optional coretemp
dev/cpuctl/cpuctl.c optional cpuctl
# There are no systems with isa slots, so all ed isa entries should go..
Modified: stable/7/sys/conf/files.i386
==============================================================================
--- stable/7/sys/conf/files.i386 Sun Jan 5 23:02:03 2014 (r260356)
+++ stable/7/sys/conf/files.i386 Sun Jan 5 23:13:18 2014 (r260357)
@@ -145,6 +145,14 @@ dev/atkbdc/atkbdc.c optional atkbdc
dev/atkbdc/atkbdc_isa.c optional atkbdc isa
dev/atkbdc/atkbdc_subr.c optional atkbdc
dev/atkbdc/psm.c optional psm atkbdc
+dev/bxe/bxe.c optional bxe pci
+dev/bxe/bxe_stats.c optional bxe pci
+dev/bxe/bxe_debug.c optional bxe pci
+dev/bxe/ecore_sp.c optional bxe pci
+dev/bxe/bxe_elink.c optional bxe pci
+dev/bxe/57710_init_values.c optional bxe pci
+dev/bxe/57711_init_values.c optional bxe pci
+dev/bxe/57712_init_values.c optional bxe pci
dev/ce/ceddk.c optional ce
dev/ce/if_ce.c optional ce
dev/ce/tau32-ddk.c optional ce
Added: stable/7/sys/dev/bxe/57710_init_values.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/7/sys/dev/bxe/57710_init_values.c Sun Jan 5 23:13:18 2014 (r260357)
@@ -0,0 +1,29161 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis <edavis at broadcom.com>
+ * David Christensen <davidch at broadcom.com>
+ * Gary Zambrano <zambrano at broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+
+/*
+* This file contains an array of operations needed to initialize the chip:
+* OP_WR - write a single register.
+* OP_RD - read a single register.
+* OP_SW - write an array to consecutive registers.
+* OP_WB - write an array using DMAE.
+* OP_ZR - clear consecutive registers.
+* OP_WB_ZR - clear consecutive registers using DMAE.
+* OP_ZP - unzip and write an array using DMAE.
+* OP_WR_64 - write a 64-bit pattern to consecutive registers.
+* OP_IF_MODE_OR - skip next ops if all modes do not match.
+* OP_IF_MODE_AND - skip next ops if at least one mode does not match.
+*/
+#include "bxe.h"
+
+#include "ecore_init.h"
+
+#ifdef __SunOS
+#define const
+#endif
+
+static const struct raw_op init_ops_e1[] = {
+/* #define BRB1_COMMON_START 22 */
+ {OP_WR, 0x600dc, 0x1},
+ {OP_SW, 0x61000, 0x2000000},
+ {OP_RD, 0x600d8, 0x0},
+ {OP_SW, 0x60200, 0x30200},
+ {OP_WR, 0x600dc, 0x0},
+/* #define BRB1_COMMON_END 23 */
+/* #define BRB1_PORT0_START 24 */
+ {OP_WR, 0x60068, 0xb8},
+ {OP_WR, 0x60078, 0x114},
+ {OP_RD, 0x600b8, 0x0},
+ {OP_RD, 0x600c8, 0x0},
+/* #define BRB1_PORT0_END 25 */
+/* #define BRB1_PORT1_START 26 */
+ {OP_WR, 0x6006c, 0xb8},
+ {OP_WR, 0x6007c, 0x114},
+ {OP_RD, 0x600bc, 0x0},
+ {OP_RD, 0x600cc, 0x0},
+/* #define BRB1_PORT1_END 27 */
+/* #define CCM_COMMON_START 44 */
+ {OP_WR, 0xd0044, 0x32},
+ {OP_SW, 0xd004c, 0x40203},
+ {OP_ZR, 0xd005c, 0x4},
+ {OP_SW, 0xd008c, 0x110207},
+ {OP_WR, 0xd015c, 0x1},
+ {OP_SW, 0xd0164, 0x20218},
+ {OP_WR, 0xd0204, 0x1},
+ {OP_SW, 0xd020c, 0x3021a},
+ {OP_SW, 0xd0220, 0x2021d},
+ {OP_ZR, 0xd0280, 0x12},
+ {OP_SW, 0xd0300, 0x18021f},
+ {OP_ZR, 0xd0360, 0xc},
+ {OP_ZR, 0xd4000, 0xa00},
+ {OP_SW, 0xd0004, 0xf0237},
+/* #define CCM_COMMON_END 45 */
+/* #define CCM_PORT0_START 46 */
+ {OP_WR, 0xd0114, 0xd},
+/* #define CCM_PORT0_END 47 */
+/* #define CCM_PORT1_START 48 */
+ {OP_WR, 0xd0118, 0x2d},
+/* #define CCM_PORT1_END 49 */
+/* #define CDU_COMMON_START 66 */
+ {OP_SW, 0x101000, 0x30246},
+ {OP_WR, 0x101010, 0x264},
+ {OP_WB, 0x101100, 0x100249},
+ {OP_WB_ZR, 0x101140, 0x8},
+ {OP_WB, 0x101160, 0x100259},
+ {OP_WB_ZR, 0x1011a0, 0x18},
+ {OP_WB, 0x101800, 0x2000269},
+ {OP_WR, 0x101010, 0x0},
+/* #define CDU_COMMON_END 67 */
+/* #define CFC_COMMON_START 88 */
+ {OP_ZR, 0x104c00, 0x100},
+ {OP_WR, 0x104028, 0x10},
+ {OP_WR, 0x104044, 0x3fff},
+ {OP_WR, 0x104058, 0x280000},
+ {OP_WR, 0x104084, 0x84924a},
+ {OP_WR, 0x104058, 0x0},
+/* #define CFC_COMMON_END 89 */
+/* #define CSDM_COMMON_START 110 */
+ {OP_SW, 0xc2008, 0x30469},
+ {OP_SW, 0xc201c, 0x4046c},
+ {OP_SW, 0xc2038, 0x110470},
+ {OP_ZR, 0xc207c, 0x4f},
+ {OP_SW, 0xc21b8, 0x110481},
+ {OP_ZR, 0xc21fc, 0xf},
+ {OP_SW, 0xc2238, 0x40492},
+ {OP_RD, 0xc2248, 0x0},
+ {OP_RD, 0xc224c, 0x0},
+ {OP_RD, 0xc2250, 0x0},
+ {OP_RD, 0xc2254, 0x0},
+ {OP_RD, 0xc2258, 0x0},
+ {OP_RD, 0xc225c, 0x0},
+ {OP_RD, 0xc2260, 0x0},
+ {OP_RD, 0xc2264, 0x0},
+ {OP_RD, 0xc2268, 0x0},
+ {OP_RD, 0xc226c, 0x0},
+ {OP_RD, 0xc2270, 0x0},
+ {OP_RD, 0xc2274, 0x0},
+ {OP_RD, 0xc2278, 0x0},
+ {OP_RD, 0xc227c, 0x0},
+ {OP_WR, 0xc24bc, 0x1},
+ {OP_IF_MODE_AND, 1, 0x1}, /* asic */
+ {OP_WR, 0xc2000, 0x3e8},
+ {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
+ {OP_WR, 0xc2000, 0xa},
+ {OP_IF_MODE_AND, 1, 0x4}, /* emul */
+ {OP_WR, 0xc2000, 0x1},
+/* #define CSDM_COMMON_END 111 */
+/* #define CSEM_COMMON_START 132 */
+ {OP_FW, 0x200400, 0xe00000},
+ {OP_WR_64, 0x200780, 0x100496},
+ {OP_ZR, 0x220000, 0x1600},
+ {OP_ZR, 0x228000, 0x40},
+ {OP_ZR, 0x223bd0, 0x8},
+ {OP_ZR, 0x224800, 0x6},
+ {OP_SW, 0x224818, 0x40498},
+ {OP_ZR, 0x224828, 0xc},
+ {OP_SW, 0x224858, 0x4049c},
+ {OP_ZR, 0x224868, 0xc},
+ {OP_SW, 0x224898, 0x404a0},
+ {OP_ZR, 0x2248a8, 0xc},
+ {OP_SW, 0x2248d8, 0x404a4},
+ {OP_ZR, 0x2248e8, 0xc},
+ {OP_SW, 0x224918, 0x404a8},
+ {OP_ZR, 0x224928, 0xc},
+ {OP_SW, 0x224958, 0x404ac},
+ {OP_ZR, 0x224968, 0xc},
+ {OP_SW, 0x224998, 0x404b0},
+ {OP_ZR, 0x2249a8, 0xc},
+ {OP_SW, 0x2249d8, 0x404b4},
+ {OP_ZR, 0x2249e8, 0xc},
+ {OP_SW, 0x224a18, 0x404b8},
+ {OP_ZR, 0x224a28, 0xc},
+ {OP_SW, 0x224a58, 0x404bc},
+ {OP_ZR, 0x224a68, 0xc},
+ {OP_SW, 0x224a98, 0x404c0},
+ {OP_ZR, 0x224aa8, 0xc},
+ {OP_SW, 0x224ad8, 0x404c4},
+ {OP_ZR, 0x224ae8, 0xc},
+ {OP_SW, 0x224b18, 0x404c8},
+ {OP_ZR, 0x224b28, 0xc},
+ {OP_SW, 0x224b58, 0x404cc},
+ {OP_ZR, 0x224b68, 0xc},
+ {OP_SW, 0x224b98, 0x404d0},
+ {OP_ZR, 0x224ba8, 0xc},
+ {OP_SW, 0x224bd8, 0x404d4},
+ {OP_ZR, 0x224be8, 0xc},
+ {OP_SW, 0x224c18, 0x404d8},
+ {OP_ZR, 0x224c28, 0xc},
+ {OP_SW, 0x224c58, 0x404dc},
+ {OP_ZR, 0x224c68, 0xc},
+ {OP_SW, 0x224c98, 0x404e0},
+ {OP_ZR, 0x224ca8, 0xc},
+ {OP_SW, 0x224cd8, 0x404e4},
+ {OP_ZR, 0x224ce8, 0xc},
+ {OP_SW, 0x224d18, 0x404e8},
+ {OP_ZR, 0x224d28, 0xc},
+ {OP_SW, 0x224d58, 0x404ec},
+ {OP_ZR, 0x224d68, 0xc},
+ {OP_SW, 0x224d98, 0x404f0},
+ {OP_ZR, 0x224da8, 0xc},
+ {OP_SW, 0x224dd8, 0x404f4},
+ {OP_ZR, 0x224de8, 0xc},
+ {OP_SW, 0x224e18, 0x404f8},
+ {OP_ZR, 0x224e28, 0xc},
+ {OP_SW, 0x224e58, 0x404fc},
+ {OP_ZR, 0x224e68, 0xc},
+ {OP_SW, 0x224e98, 0x40500},
+ {OP_ZR, 0x224ea8, 0xc},
+ {OP_SW, 0x224ed8, 0x40504},
+ {OP_ZR, 0x224ee8, 0xc},
+ {OP_SW, 0x224f18, 0x40508},
+ {OP_ZR, 0x224f28, 0xc},
+ {OP_SW, 0x224f58, 0x4050c},
+ {OP_ZR, 0x224f68, 0xc},
+ {OP_SW, 0x224f98, 0x40510},
+ {OP_ZR, 0x224fa8, 0xc},
+ {OP_SW, 0x224fd8, 0x40514},
+ {OP_ZR, 0x224fe8, 0x6},
+ {OP_SW, 0x225198, 0x40518},
+ {OP_WR, 0x238000, 0x10},
+ {OP_WR, 0x238040, 0x12},
+ {OP_WR, 0x238080, 0x30},
+ {OP_WR, 0x2380c0, 0xe},
+ {OP_WR, 0x238380, 0x7a120},
+ {OP_WR, 0x2383c0, 0x1f4},
+ {OP_WR, 0x238bc0, 0x1},
+ {OP_IF_MODE_AND, 2, 0x1}, /* asic */
+ {OP_WR, 0x238300, 0x7a120},
+ {OP_WR, 0x238340, 0x1f4},
+ {OP_IF_MODE_AND, 2, 0x2}, /* fpga */
+ {OP_WR, 0x238300, 0x1388},
+ {OP_WR, 0x238340, 0x5},
+ {OP_IF_MODE_AND, 2, 0x4}, /* emul */
+ {OP_WR, 0x238300, 0x138},
+ {OP_WR, 0x238340, 0x0},
+ {OP_FW, 0x240000, 0x27300000},
+ {OP_WR_64, 0x249cc0, 0x6ace051c},
+ {OP_RD, 0x200000, 0x0},
+ {OP_RD, 0x200004, 0x0},
+ {OP_RD, 0x200008, 0x0},
+ {OP_RD, 0x20000c, 0x0},
+ {OP_RD, 0x200010, 0x0},
+ {OP_RD, 0x200014, 0x0},
+ {OP_SW, 0x200020, 0x1a051e},
+ {OP_SW, 0x2000a4, 0x20538},
+ {OP_WR, 0x200224, 0x0},
+ {OP_WR, 0x200234, 0x0},
+ {OP_WR, 0x20024c, 0x0},
+ {OP_WR, 0x2002e4, 0xffff},
+ {OP_WB_ZR, 0x202000, 0x800},
+/* #define CSEM_COMMON_END 133 */
+/* #define CSEM_PORT0_START 134 */
+ {OP_ZR, 0x221400, 0x2},
+ {OP_ZR, 0x221490, 0x30},
+ {OP_ZR, 0x223900, 0x10},
+ {OP_ZR, 0x225108, 0x2},
+ {OP_ZR, 0x2251a8, 0x6},
+/* #define CSEM_PORT0_END 135 */
+/* #define CSEM_PORT1_START 136 */
+ {OP_ZR, 0x221408, 0x2},
+ {OP_ZR, 0x221550, 0x30},
+ {OP_ZR, 0x223940, 0x10},
+ {OP_ZR, 0x225110, 0x2},
+ {OP_ZR, 0x2251c0, 0x6},
+/* #define CSEM_PORT1_END 137 */
+/* #define DMAE_COMMON_START 176 */
+ {OP_ZR, 0x102400, 0xe0},
+ {OP_SW, 0x10201c, 0x2053a},
+ {OP_WR, 0x1020c0, 0x1},
+ {OP_SW, 0x102004, 0x2053c},
+/* #define DMAE_COMMON_END 177 */
+/* #define DORQ_COMMON_START 198 */
+ {OP_WR, 0x170008, 0x2},
+ {OP_WR, 0x17002c, 0x3},
+ {OP_SW, 0x170038, 0x2053e},
+ {OP_SW, 0x170044, 0x60540},
+ {OP_SW, 0x170060, 0x50546},
+ {OP_SW, 0x170078, 0x2054b},
+ {OP_WR, 0x170004, 0xf},
+/* #define DORQ_COMMON_END 199 */
+/* #define HC_COMMON_START 220 */
+ {OP_ZR, 0x108068, 0x4},
+/* #define HC_COMMON_END 221 */
+/* #define HC_PORT0_START 222 */
+ {OP_WR, 0x108000, 0x1080},
+ {OP_ZR, 0x108040, 0x2},
+ {OP_ZR, 0x108028, 0x2},
+ {OP_WR, 0x108038, 0x10},
+ {OP_SW, 0x108040, 0x2054d},
+ {OP_WR, 0x108050, 0x0},
+ {OP_WR, 0x108100, 0x0},
+ {OP_ZR, 0x108120, 0x2},
+ {OP_WR, 0x108008, 0x2b5},
+ {OP_WR, 0x108010, 0x0},
+ {OP_WR, 0x108108, 0x1ffff},
+ {OP_ZR, 0x108200, 0x4a},
+ {OP_ZR, 0x108140, 0x2},
+ {OP_WR, 0x108000, 0x1a80},
+ {OP_ZR, 0x109000, 0x24},
+ {OP_ZR, 0x109120, 0x4a},
+ {OP_ZR, 0x109370, 0x4a},
+ {OP_ZR, 0x1095c0, 0x4a},
+/* #define HC_PORT0_END 223 */
+/* #define HC_PORT1_START 224 */
+ {OP_WR, 0x108004, 0x1080},
+ {OP_ZR, 0x108048, 0x2},
+ {OP_ZR, 0x108030, 0x2},
+ {OP_WR, 0x10803c, 0x10},
+ {OP_SW, 0x108048, 0x2054f},
+ {OP_WR, 0x108054, 0x0},
+ {OP_WR, 0x108104, 0x0},
+ {OP_ZR, 0x108128, 0x2},
+ {OP_WR, 0x10800c, 0x2b5},
+ {OP_WR, 0x108014, 0x0},
+ {OP_WR, 0x10810c, 0x1ffff},
+ {OP_ZR, 0x108400, 0x4a},
+ {OP_ZR, 0x108148, 0x2},
+ {OP_WR, 0x108004, 0x1a80},
+ {OP_ZR, 0x109090, 0x24},
+ {OP_ZR, 0x109248, 0x4a},
+ {OP_ZR, 0x109498, 0x4a},
+ {OP_ZR, 0x1096e8, 0x4a},
+/* #define HC_PORT1_END 225 */
+/* #define MISC_COMMON_START 264 */
+ {OP_WR, 0xa468, 0xaffdc},
+ {OP_WR, 0xa280, 0x1},
+ {OP_SW, 0xa294, 0x40551},
+ {OP_WR, 0xa4fc, 0xff000000},
+/* #define MISC_COMMON_END 265 */
+/* #define NIG_COMMON_START 286 */
+ {OP_SW, 0x100b4, 0x20555},
+ {OP_WR, 0x100dc, 0x1},
+ {OP_SW, 0x10100, 0x20557},
+/* #define NIG_COMMON_END 287 */
+/* #define NIG_PORT0_START 288 */
+ {OP_WR, 0x1007c, 0x300000},
+ {OP_WR, 0x10084, 0x28},
+ {OP_WR, 0x1008c, 0x0},
+ {OP_WR, 0x10130, 0x4},
+ {OP_ZR, 0x10138, 0x11},
+ {OP_WR, 0x10328, 0x0},
+ {OP_WR, 0x10554, 0x30},
+ {OP_WR, 0x100c4, 0x1},
+ {OP_WR, 0x100cc, 0x1},
+ {OP_WR, 0x100f8, 0x1},
+ {OP_WR, 0x100f0, 0x1},
+/* #define NIG_PORT0_END 289 */
+/* #define NIG_PORT1_START 290 */
+ {OP_WR, 0x10080, 0x300000},
+ {OP_WR, 0x10088, 0x28},
+ {OP_WR, 0x10090, 0x0},
+ {OP_WR, 0x10134, 0x4},
+ {OP_ZR, 0x1017c, 0x11},
+ {OP_WR, 0x1032c, 0x0},
+ {OP_WR, 0x10564, 0x30},
+ {OP_WR, 0x100c8, 0x1},
+ {OP_WR, 0x100d0, 0x1},
+ {OP_WR, 0x100fc, 0x1},
+ {OP_WR, 0x100f4, 0x1},
+/* #define NIG_PORT1_END 291 */
+/* #define PBF_COMMON_START 308 */
+ {OP_WR, 0x140000, 0x1},
+ {OP_WR, 0x14000c, 0x1},
+ {OP_SW, 0x140040, 0x20559},
+ {OP_WR, 0x14000c, 0x0},
+ {OP_WR, 0x140000, 0x0},
+ {OP_WR, 0x14006c, 0x0},
+/* #define PBF_COMMON_END 309 */
+/* #define PBF_PORT0_START 310 */
+ {OP_WR, 0x140004, 0x1},
+ {OP_WR, 0x140030, 0x1},
+ {OP_WR, 0x140004, 0x0},
+ {OP_WR, 0x14005c, 0x0},
+/* #define PBF_PORT0_END 311 */
+/* #define PBF_PORT1_START 312 */
+ {OP_WR, 0x140008, 0x1},
+ {OP_WR, 0x140034, 0x1},
+ {OP_WR, 0x140008, 0x0},
+ {OP_WR, 0x140060, 0x0},
+/* #define PBF_PORT1_END 313 */
+/* #define PRS_COMMON_START 352 */
+ {OP_SW, 0x40004, 0x12055b},
+ {OP_SW, 0x40054, 0x3056d},
+ {OP_WR, 0x40070, 0x4},
+ {OP_SW, 0x40078, 0x40570},
+ {OP_ZR, 0x40088, 0x5},
+ {OP_SW, 0x4009c, 0x30574},
+ {OP_ZR, 0x400a8, 0x4},
+ {OP_SW, 0x400b8, 0x50577},
+ {OP_ZR, 0x400cc, 0x4},
+ {OP_SW, 0x400dc, 0x4057c},
+ {OP_ZR, 0x400ec, 0x4},
+ {OP_RD, 0x40124, 0x0},
+ {OP_RD, 0x40128, 0x0},
+ {OP_RD, 0x4012c, 0x0},
+ {OP_RD, 0x40130, 0x0},
+ {OP_WR, 0x40134, 0xf},
+/* #define PRS_COMMON_END 353 */
+/* #define PXP2_COMMON_START 374 */
+ {OP_SW, 0x120490, 0x220580},
+ {OP_WR, 0x120520, 0x2},
+ {OP_WR, 0x120388, 0x64},
+ {OP_WR, 0x120390, 0x8},
+ {OP_SW, 0x12039c, 0x305a2},
+ {OP_WR, 0x1203bc, 0x4},
+ {OP_WR, 0x1203c4, 0x4},
+ {OP_WR, 0x1203d0, 0x0},
+ {OP_WR, 0x1203dc, 0x0},
+ {OP_WR, 0x12036c, 0x1},
+ {OP_WR, 0x120368, 0x3f},
+ {OP_SW, 0x1201bc, 0x3c05a5},
+ {OP_SW, 0x1202b0, 0x205e1},
+ {OP_SW, 0x120324, 0x205e3},
+ {OP_WR, 0x1201b0, 0x1},
+/* #define PXP2_COMMON_END 375 */
+/* #define PXP_COMMON_START 396 */
+ {OP_WB, 0x103800, 0x505e5},
+ {OP_WB, 0x103c00, 0x505ea},
+ {OP_WB, 0x103c20, 0x505ef},
+/* #define PXP_COMMON_END 397 */
+/* #define QM_COMMON_START 418 */
+ {OP_SW, 0x168030, 0x805f4},
+ {OP_WR, 0x168054, 0x2},
+ {OP_SW, 0x168060, 0x505fc},
+ {OP_ZR, 0x168074, 0x7},
+ {OP_SW, 0x168090, 0x20601},
+ {OP_SW, 0x16809c, 0x50603},
+ {OP_ZR, 0x1680b0, 0x7},
+ {OP_SW, 0x1680cc, 0x80608},
+ {OP_WR, 0x1680f0, 0x7},
+ {OP_ZR, 0x1680f4, 0xc},
+ {OP_SW, 0x168124, 0x40610},
+ {OP_ZR, 0x168134, 0xc},
+ {OP_SW, 0x168164, 0x3b0614},
+ {OP_ZR, 0x168250, 0x4},
+ {OP_SW, 0x168260, 0x2064f},
+ {OP_ZR, 0x168268, 0x8},
+ {OP_SW, 0x168288, 0x80651},
+ {OP_ZR, 0x1682a8, 0xa},
+ {OP_WR, 0x168804, 0x4},
+ {OP_SW, 0x16880c, 0x100659},
+ {OP_WR, 0x1680ec, 0xff},
+/* #define QM_COMMON_END 419 */
+/* #define SRC_COMMON_START 440 */
+ {OP_SW, 0x40408, 0x140669},
+/* #define SRC_COMMON_END 441 */
+/* #define TCM_COMMON_START 462 */
+ {OP_SW, 0x50044, 0x2067d},
+ {OP_SW, 0x50050, 0x4067f},
+ {OP_ZR, 0x50060, 0x4},
+ {OP_SW, 0x50090, 0x130683},
+ {OP_WR, 0x50114, 0x1},
+ {OP_SW, 0x5011c, 0x20696},
+ {OP_WR, 0x50204, 0x1},
+ {OP_SW, 0x5020c, 0x20698},
+ {OP_SW, 0x5021c, 0x3069a},
+ {OP_ZR, 0x50240, 0xa},
+ {OP_SW, 0x50280, 0x20069d},
+ {OP_ZR, 0x54000, 0xd00},
+ {OP_SW, 0x50004, 0x1006bd},
+/* #define TCM_COMMON_END 463 */
+/* #define TCM_PORT0_START 464 */
+ {OP_WR, 0x500e0, 0xe},
+/* #define TCM_PORT0_END 465 */
+/* #define TCM_PORT1_START 466 */
+ {OP_WR, 0x500e4, 0x2e},
+/* #define TCM_PORT1_END 467 */
+/* #define TM_COMMON_START 484 */
+ {OP_ZR, 0x164024, 0x2},
+ {OP_SW, 0x164030, 0x306cd},
+ {OP_WR, 0x164044, 0x20},
+ {OP_WR, 0x164070, 0x1c},
+ {OP_WR, 0x164208, 0x1},
+ {OP_WR, 0x164210, 0x1},
+ {OP_WR, 0x164220, 0x1},
+ {OP_WR, 0x164228, 0x1},
+ {OP_WR, 0x164230, 0x1},
+ {OP_WR, 0x164238, 0x1},
+ {OP_WR, 0x164260, 0x1},
+ {OP_IF_MODE_AND, 1, 0x1}, /* asic */
+ {OP_WR, 0x16401c, 0x3d090},
+ {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
+ {OP_WR, 0x16401c, 0x9c4},
+ {OP_IF_MODE_AND, 1, 0x4}, /* emul */
+ {OP_WR, 0x16401c, 0x9c},
+ {OP_WR, 0x164000, 0x1},
+ {OP_WR, 0x1640d8, 0x1},
+ {OP_SW, 0x164008, 0x306d0},
+/* #define TM_COMMON_END 485 */
+/* #define TM_PORT0_START 486 */
+ {OP_WR, 0x164240, 0x0},
+ {OP_WR, 0x164248, 0x0},
+ {OP_WB_ZR, 0x164270, 0x2},
+/* #define TM_PORT0_END 487 */
+/* #define TM_PORT1_START 488 */
+ {OP_WR, 0x164250, 0x0},
+ {OP_WR, 0x164258, 0x0},
+ {OP_WB_ZR, 0x164280, 0x2},
+/* #define TM_PORT1_END 489 */
+/* #define TSDM_COMMON_START 506 */
+ {OP_SW, 0x42008, 0x406d3},
+ {OP_SW, 0x4201c, 0x406d7},
+ {OP_ZR, 0x42038, 0x80},
+ {OP_SW, 0x42238, 0x406db},
+ {OP_RD, 0x42248, 0x0},
+ {OP_RD, 0x4224c, 0x0},
+ {OP_RD, 0x42250, 0x0},
+ {OP_RD, 0x42254, 0x0},
+ {OP_RD, 0x42258, 0x0},
+ {OP_RD, 0x4225c, 0x0},
+ {OP_RD, 0x42260, 0x0},
+ {OP_RD, 0x42264, 0x0},
+ {OP_RD, 0x42268, 0x0},
+ {OP_RD, 0x4226c, 0x0},
+ {OP_RD, 0x42270, 0x0},
+ {OP_RD, 0x42274, 0x0},
+ {OP_RD, 0x42278, 0x0},
+ {OP_RD, 0x4227c, 0x0},
+ {OP_WR, 0x424bc, 0x1},
+ {OP_IF_MODE_AND, 1, 0x1}, /* asic */
+ {OP_WR, 0x42000, 0x3e8},
+ {OP_IF_MODE_AND, 1, 0x2}, /* fpga */
+ {OP_WR, 0x42000, 0xa},
+ {OP_IF_MODE_AND, 1, 0x4}, /* emul */
+ {OP_WR, 0x42000, 0x1},
+/* #define TSDM_COMMON_END 507 */
+/* #define TSEM_COMMON_START 528 */
+ {OP_FW, 0x180400, 0xd80000},
+ {OP_WR_64, 0x180760, 0x1406df},
+ {OP_ZR, 0x1a0000, 0x1600},
+ {OP_ZR, 0x1a8000, 0x40},
+ {OP_SW, 0x1a08b0, 0x206e1},
+ {OP_SW, 0x1a19c8, 0x206e3},
+ {OP_SW, 0x1a2fc0, 0x406e5},
+ {OP_ZR, 0x1a2fd0, 0x6},
+ {OP_SW, 0x1a2fe8, 0x206e9},
+ {OP_SW, 0x1a3000, 0x3f906eb},
+ {OP_ZR, 0x1a3fe4, 0x7},
+ {OP_SW, 0x1a4870, 0x40ae4},
+ {OP_WR, 0x1b8000, 0x34},
+ {OP_WR, 0x1b8040, 0x18},
+ {OP_WR, 0x1b8080, 0xc},
+ {OP_WR, 0x1b80c0, 0x20},
+ {OP_WR, 0x1b8380, 0x7a120},
+ {OP_WR, 0x1b83c0, 0x1f4},
+ {OP_WR, 0x1b8bc0, 0x1},
+ {OP_IF_MODE_AND, 2, 0x1}, /* asic */
+ {OP_WR, 0x1b8300, 0x7a120},
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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