svn commit: r276070 - in stable/10/sys: amd64/amd64 amd64/include conf i386/i386 i386/include pc98/pc98 x86/x86

John Baldwin jhb at FreeBSD.org
Mon Dec 22 18:41:04 UTC 2014


Author: jhb
Date: Mon Dec 22 18:40:59 2014
New Revision: 276070
URL: https://svnweb.freebsd.org/changeset/base/276070

Log:
  MFC 260557,271076,271077,271082,271083,271098:
  - Remove spaces from boot messages when we print the CPU ID/Family/Stepping
  - Move prototypes for various functions into out of C files and into
    <machine/md_var.h>.
  - Reduce diffs between i386 and amd64 initcpu.c and identcpu.c files.
  - Move blacklists of broken TSCs out of the printcpuinfo() function
    and into the TSC probe routine.
  - Merge the amd64 and i386 identcpu.c into a single x86 implementation.

Added:
  stable/10/sys/x86/x86/identcpu.c
     - copied unchanged from r271098, head/sys/x86/x86/identcpu.c
Deleted:
  stable/10/sys/amd64/amd64/identcpu.c
  stable/10/sys/i386/i386/identcpu.c
Modified:
  stable/10/sys/amd64/amd64/machdep.c
  stable/10/sys/amd64/include/md_var.h
  stable/10/sys/conf/files.amd64
  stable/10/sys/conf/files.i386
  stable/10/sys/conf/files.pc98
  stable/10/sys/i386/i386/initcpu.c
  stable/10/sys/i386/i386/machdep.c
  stable/10/sys/i386/i386/trap.c
  stable/10/sys/i386/include/md_var.h
  stable/10/sys/pc98/pc98/machdep.c
  stable/10/sys/x86/x86/tsc.c
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/amd64/amd64/machdep.c
==============================================================================
--- stable/10/sys/amd64/amd64/machdep.c	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/amd64/amd64/machdep.c	Mon Dec 22 18:40:59 2014	(r276070)
@@ -153,10 +153,6 @@ CTASSERT(offsetof(struct pcpu, pc_curthr
 
 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
 
-extern void printcpuinfo(void);	/* XXX header file */
-extern void identify_cpu(void);
-extern void panicifcpuunsupported(void);
-
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 

Modified: stable/10/sys/amd64/include/md_var.h
==============================================================================
--- stable/10/sys/amd64/include/md_var.h	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/amd64/include/md_var.h	Mon Dec 22 18:40:59 2014	(r276070)
@@ -105,14 +105,17 @@ void	fsbase_load_fault(void) __asm(__STR
 void	gsbase_load_fault(void) __asm(__STRING(gsbase_load_fault));
 void	dump_add_page(vm_paddr_t);
 void	dump_drop_page(vm_paddr_t);
+void	identify_cpu(void);
 void	initializecpu(void);
 void	initializecpucache(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
 void	fpstate_drop(struct thread *td);
 int	is_physical_memory(vm_paddr_t addr);
 int	isa_nmi(int cd);
+void	panicifcpuunsupported(void);
 void	pagecopy(void *from, void *to);
 void	pagezero(void *addr);
+void	printcpuinfo(void);
 void	setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int ist);
 int	user_dbreg_trap(void);
 void	minidumpsys(struct dumperinfo *);

Modified: stable/10/sys/conf/files.amd64
==============================================================================
--- stable/10/sys/conf/files.amd64	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/conf/files.amd64	Mon Dec 22 18:40:59 2014	(r276070)
@@ -114,7 +114,6 @@ amd64/amd64/elf_machdep.c	standard
 amd64/amd64/exception.S		standard
 amd64/amd64/fpu.c		standard
 amd64/amd64/gdb_machdep.c	optional	gdb
-amd64/amd64/identcpu.c		standard
 amd64/amd64/in_cksum.c		optional	inet | inet6
 amd64/amd64/initcpu.c		standard
 amd64/amd64/io.c		optional	io
@@ -578,6 +577,7 @@ x86/x86/busdma_bounce.c		standard
 x86/x86/busdma_machdep.c	standard
 x86/x86/dump_machdep.c		standard
 x86/x86/fdt_machdep.c		optional	fdt
+x86/x86/identcpu.c		standard
 x86/x86/intr_machdep.c		standard
 x86/x86/io_apic.c		standard
 x86/x86/legacy.c		standard

Modified: stable/10/sys/conf/files.i386
==============================================================================
--- stable/10/sys/conf/files.i386	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/conf/files.i386	Mon Dec 22 18:40:59 2014	(r276070)
@@ -460,7 +460,6 @@ i386/xen/exception.s		optional xen
 i386/i386/gdb_machdep.c		optional gdb
 i386/i386/geode.c		optional cpu_geode
 i386/i386/i686_mem.c		optional mem
-i386/i386/identcpu.c		standard
 i386/i386/in_cksum.c		optional inet | inet6
 i386/i386/initcpu.c		standard
 i386/i386/io.c			optional io
@@ -594,6 +593,7 @@ x86/x86/busdma_bounce.c		standard
 x86/x86/busdma_machdep.c	standard
 x86/x86/dump_machdep.c		standard
 x86/x86/fdt_machdep.c		optional fdt
+x86/x86/identcpu.c		standard
 x86/x86/intr_machdep.c		standard
 x86/x86/io_apic.c		optional apic
 x86/x86/legacy.c		optional native

Modified: stable/10/sys/conf/files.pc98
==============================================================================
--- stable/10/sys/conf/files.pc98	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/conf/files.pc98	Mon Dec 22 18:40:59 2014	(r276070)
@@ -143,7 +143,6 @@ i386/i386/elf_machdep.c		standard
 i386/i386/exception.s		standard
 i386/i386/gdb_machdep.c		optional gdb
 i386/i386/i686_mem.c		optional mem
-i386/i386/identcpu.c		standard
 i386/i386/in_cksum.c		optional inet | inet6
 i386/i386/initcpu.c		standard
 i386/i386/io.c			optional io
@@ -251,6 +250,7 @@ x86/pci/pci_bus.c		optional pci
 x86/x86/busdma_bounce.c		standard
 x86/x86/busdma_machdep.c	standard
 x86/x86/dump_machdep.c		standard
+x86/x86/identcpu.c		standard
 x86/x86/intr_machdep.c		standard
 x86/x86/io_apic.c		optional apic
 x86/x86/legacy.c		standard

Modified: stable/10/sys/i386/i386/initcpu.c
==============================================================================
--- stable/10/sys/i386/i386/initcpu.c	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/i386/i386/initcpu.c	Mon Dec 22 18:40:59 2014	(r276070)
@@ -48,12 +48,6 @@ __FBSDID("$FreeBSD$");
 #define CPU_ENABLE_SSE
 #endif
 
-#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
-void	enable_K5_wt_alloc(void);
-void	enable_K6_wt_alloc(void);
-void	enable_K6_2_wt_alloc(void);
-#endif
-
 #ifdef I486_CPU
 static void init_5x86(void);
 static void init_bluelightning(void);
@@ -81,36 +75,37 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_ss
  */
 static int	hw_clflush_disable = -1;
 
-/* Must *NOT* be BSS or locore will bzero these after setting them */
-int	cpu = 0;		/* Are we 386, 386sx, 486, etc? */
-u_int	cpu_feature = 0;	/* Feature flags */
-u_int	cpu_feature2 = 0;	/* Feature flags */
-u_int	amd_feature = 0;	/* AMD feature flags */
-u_int	amd_feature2 = 0;	/* AMD feature flags */
-u_int	amd_pminfo = 0;		/* AMD advanced power management info */
-u_int	via_feature_rng = 0;	/* VIA RNG features */
-u_int	via_feature_xcrypt = 0;	/* VIA ACE features */
-u_int	cpu_high = 0;		/* Highest arg to CPUID */
-u_int	cpu_id = 0;		/* Stepping ID */
-u_int	cpu_procinfo = 0;	/* HyperThreading Info / Brand Index / CLFUSH */
-u_int	cpu_procinfo2 = 0;	/* Multicore info */
-char	cpu_vendor[20] = "";	/* CPU Origin code */
-u_int	cpu_vendor_id = 0;	/* CPU vendor ID */
+int	cpu;			/* Are we 386, 386sx, 486, etc? */
+u_int	cpu_feature;		/* Feature flags */
+u_int	cpu_feature2;		/* Feature flags */
+u_int	amd_feature;		/* AMD feature flags */
+u_int	amd_feature2;		/* AMD feature flags */
+u_int	amd_pminfo;		/* AMD advanced power management info */
+u_int	via_feature_rng;	/* VIA RNG features */
+u_int	via_feature_xcrypt;	/* VIA ACE features */
+u_int	cpu_high;		/* Highest arg to CPUID */
+u_int	cpu_exthigh;		/* Highest arg to extended CPUID */
+u_int	cpu_id;			/* Stepping ID */
+u_int	cpu_procinfo;		/* HyperThreading Info / Brand Index / CLFUSH */
+u_int	cpu_procinfo2;		/* Multicore info */
+char	cpu_vendor[20];		/* CPU Origin code */
+u_int	cpu_vendor_id;		/* CPU vendor ID */
+#ifdef CPU_ENABLE_SSE
+u_int	cpu_fxsr;		/* SSE enabled */
+u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
+#endif
 u_int	cpu_clflush_line_size = 32;
+u_int	cpu_stdext_feature;
 u_int	cpu_mon_mwait_flags;	/* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 u_int	cpu_mon_min_size;	/* MONITOR minimum range size, bytes */
 u_int	cpu_mon_max_size;	/* MONITOR minimum range size, bytes */
+u_int	cyrix_did;		/* Device ID of Cyrix CPU */
 
 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 	&via_feature_rng, 0, "VIA RNG feature available in CPU");
 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 	&via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
 
-#ifdef CPU_ENABLE_SSE
-u_int	cpu_fxsr;		/* SSE enabled */
-u_int	cpu_mxcsr_mask;		/* valid bits in mxcsr */
-#endif
-
 #ifdef I486_CPU
 /*
  * IBM Blue Lightning

Modified: stable/10/sys/i386/i386/machdep.c
==============================================================================
--- stable/10/sys/i386/i386/machdep.c	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/i386/i386/machdep.c	Mon Dec 22 18:40:59 2014	(r276070)
@@ -182,10 +182,6 @@ CTASSERT(offsetof(struct pcpu, pc_curthr
 extern void init386(int first);
 extern void dblfault_handler(void);
 
-extern void printcpuinfo(void);	/* XXX header file */
-extern void finishidentcpu(void);
-extern void panicifcpuunsupported(void);
-
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 
@@ -1664,10 +1660,6 @@ struct gate_descriptor *idt = &idt0[0];	
 struct region_descriptor r_gdt, r_idt;	/* table descriptors */
 struct mtx dt_lock;			/* lock for GDT and LDT */
 
-#if defined(I586_CPU) && !defined(NO_F00F_HACK)
-extern int has_f00f_bug;
-#endif
-
 static struct i386tss dblfault_tss;
 static char dblfault_stack[PAGE_SIZE];
 

Modified: stable/10/sys/i386/i386/trap.c
==============================================================================
--- stable/10/sys/i386/i386/trap.c	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/i386/i386/trap.c	Mon Dec 22 18:40:59 2014	(r276070)
@@ -154,7 +154,7 @@ static char *trap_msg[] = {
 };
 
 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
-extern int has_f00f_bug;
+int has_f00f_bug = 0;		/* Initialized so that it can be patched. */
 #endif
 
 #ifdef KDB

Modified: stable/10/sys/i386/include/md_var.h
==============================================================================
--- stable/10/sys/i386/include/md_var.h	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/i386/include/md_var.h	Mon Dec 22 18:40:59 2014	(r276070)
@@ -48,6 +48,7 @@ extern	u_int	amd_pminfo;
 extern	u_int	via_feature_rng;
 extern	u_int	via_feature_xcrypt;
 extern	u_int	cpu_clflush_line_size;
+extern	u_int	cpu_stdext_feature;
 extern	u_int	cpu_fxsr;
 extern	u_int	cpu_high;
 extern	u_int	cpu_id;
@@ -56,10 +57,13 @@ extern	u_int	cpu_procinfo;
 extern	u_int	cpu_procinfo2;
 extern	char	cpu_vendor[];
 extern	u_int	cpu_vendor_id;
-extern	u_int	cyrix_did;
 extern	u_int	cpu_mon_mwait_flags;
 extern	u_int	cpu_mon_min_size;
 extern	u_int	cpu_mon_max_size;
+extern	u_int	cyrix_did;
+#if defined(I586_CPU) && !defined(NO_F00F_HACK)
+extern	int	has_f00f_bug;
+#endif
 extern	char	kstack[];
 extern	char	sigcode[];
 extern	int	szsigcode;
@@ -94,15 +98,23 @@ void	doreti_popl_fs(void) __asm(__STRING
 void	doreti_popl_fs_fault(void) __asm(__STRING(doreti_popl_fs_fault));
 void	dump_add_page(vm_paddr_t);
 void	dump_drop_page(vm_paddr_t);
-void	initializecpu(void);
+void	finishidentcpu(void);
+#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
+void	enable_K5_wt_alloc(void);
+void	enable_K6_wt_alloc(void);
+void	enable_K6_2_wt_alloc(void);
+#endif
 void	enable_sse(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
+void	initializecpu(void);
 void	i686_pagezero(void *addr);
 void	sse2_pagezero(void *addr);
 void	init_AMD_Elan_sc520(void);
 int	is_physical_memory(vm_paddr_t addr);
 int	isa_nmi(int cd);
 vm_paddr_t kvtop(void *addr);
+void	panicifcpuunsupported(void);
+void	printcpuinfo(void);
 void	setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int selec);
 int     user_dbreg_trap(void);
 void	minidumpsys(struct dumperinfo *);

Modified: stable/10/sys/pc98/pc98/machdep.c
==============================================================================
--- stable/10/sys/pc98/pc98/machdep.c	Mon Dec 22 18:39:38 2014	(r276069)
+++ stable/10/sys/pc98/pc98/machdep.c	Mon Dec 22 18:40:59 2014	(r276070)
@@ -151,10 +151,6 @@ CTASSERT(offsetof(struct pcpu, pc_curthr
 extern void init386(int first);
 extern void dblfault_handler(void);
 
-extern void printcpuinfo(void);	/* XXX header file */
-extern void finishidentcpu(void);
-extern void panicifcpuunsupported(void);
-
 #define	CS_SECURE(cs)		(ISPL(cs) == SEL_UPL)
 #define	EFL_SECURE(ef, oef)	((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
 

Copied: stable/10/sys/x86/x86/identcpu.c (from r271098, head/sys/x86/x86/identcpu.c)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ stable/10/sys/x86/x86/identcpu.c	Mon Dec 22 18:40:59 2014	(r276070, copy of r271098, head/sys/x86/x86/identcpu.c)
@@ -0,0 +1,1989 @@
+/*-
+ * Copyright (c) 1992 Terrence R. Lambert.
+ * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
+ * Copyright (c) 1997 KATO Takenori.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_cpu.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/eventhandler.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/sysctl.h>
+#include <sys/power.h>
+
+#include <machine/asmacros.h>
+#include <machine/clock.h>
+#include <machine/cputypes.h>
+#include <machine/frame.h>
+#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
+#include <machine/segments.h>
+#include <machine/specialreg.h>
+
+#include <amd64/vmm/intel/vmx_controls.h>
+#include <x86/isa/icu.h>
+
+#ifdef __i386__
+#define	IDENTBLUE_CYRIX486	0
+#define	IDENTBLUE_IBMCPU	1
+#define	IDENTBLUE_CYRIXM2	2
+
+static void identifycyrix(void);
+static void print_transmeta_info(void);
+#endif
+static u_int find_cpu_vendor_id(void);
+static void print_AMD_info(void);
+static void print_INTEL_info(void);
+static void print_INTEL_TLB(u_int data);
+static void print_via_padlock_info(void);
+static void print_vmx_info(void);
+
+int	cpu_class;
+char machine[] = MACHINE;
+
+#ifdef __amd64__
+#ifdef SCTL_MASK32
+extern int adaptive_machine_arch;
+#endif
+
+static int
+sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
+{
+#ifdef SCTL_MASK32
+	static const char machine32[] = "i386";
+#endif
+	int error;
+
+#ifdef SCTL_MASK32
+	if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
+		error = SYSCTL_OUT(req, machine32, sizeof(machine32));
+	else
+#endif
+		error = SYSCTL_OUT(req, machine, sizeof(machine));
+	return (error);
+
+}
+SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
+    NULL, 0, sysctl_hw_machine, "A", "Machine class");
+#else
+SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
+    machine, 0, "Machine class");
+#endif
+
+static char cpu_model[128];
+SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
+    cpu_model, 0, "Machine model");
+
+static int hw_clockrate;
+SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
+    &hw_clockrate, 0, "CPU instruction clock rate");
+
+static eventhandler_tag tsc_post_tag;
+
+static char cpu_brand[48];
+
+#ifdef __i386__
+#define	MAX_BRAND_INDEX	8
+
+static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
+	NULL,			/* No brand */
+	"Intel Celeron",
+	"Intel Pentium III",
+	"Intel Pentium III Xeon",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"Intel Pentium 4"
+};
+#endif
+
+static struct {
+	char	*cpu_name;
+	int	cpu_class;
+} cpus[] = {
+#ifdef __i386__
+	{ "Intel 80286",	CPUCLASS_286 },		/* CPU_286   */
+	{ "i386SX",		CPUCLASS_386 },		/* CPU_386SX */
+	{ "i386DX",		CPUCLASS_386 },		/* CPU_386   */
+	{ "i486SX",		CPUCLASS_486 },		/* CPU_486SX */
+	{ "i486DX",		CPUCLASS_486 },		/* CPU_486   */
+	{ "Pentium",		CPUCLASS_586 },		/* CPU_586   */
+	{ "Cyrix 486",		CPUCLASS_486 },		/* CPU_486DLC */
+	{ "Pentium Pro",	CPUCLASS_686 },		/* CPU_686 */
+	{ "Cyrix 5x86",		CPUCLASS_486 },		/* CPU_M1SC */
+	{ "Cyrix 6x86",		CPUCLASS_486 },		/* CPU_M1 */
+	{ "Blue Lightning",	CPUCLASS_486 },		/* CPU_BLUE */
+	{ "Cyrix 6x86MX",	CPUCLASS_686 },		/* CPU_M2 */
+	{ "NexGen 586",		CPUCLASS_386 },		/* CPU_NX586 (XXX) */
+	{ "Cyrix 486S/DX",	CPUCLASS_486 },		/* CPU_CY486DX */
+	{ "Pentium II",		CPUCLASS_686 },		/* CPU_PII */
+	{ "Pentium III",	CPUCLASS_686 },		/* CPU_PIII */
+	{ "Pentium 4",		CPUCLASS_686 },		/* CPU_P4 */
+#else
+	{ "Clawhammer",		CPUCLASS_K8 },		/* CPU_CLAWHAMMER */
+	{ "Sledgehammer",	CPUCLASS_K8 },		/* CPU_SLEDGEHAMMER */
+#endif
+};
+
+static struct {
+	char	*vendor;
+	u_int	vendor_id;
+} cpu_vendors[] = {
+	{ INTEL_VENDOR_ID,	CPU_VENDOR_INTEL },	/* GenuineIntel */
+	{ AMD_VENDOR_ID,	CPU_VENDOR_AMD },	/* AuthenticAMD */
+	{ CENTAUR_VENDOR_ID,	CPU_VENDOR_CENTAUR },	/* CentaurHauls */
+#ifdef __i386__
+	{ NSC_VENDOR_ID,	CPU_VENDOR_NSC },	/* Geode by NSC */
+	{ CYRIX_VENDOR_ID,	CPU_VENDOR_CYRIX },	/* CyrixInstead */
+	{ TRANSMETA_VENDOR_ID,	CPU_VENDOR_TRANSMETA },	/* GenuineTMx86 */
+	{ SIS_VENDOR_ID,	CPU_VENDOR_SIS },	/* SiS SiS SiS  */
+	{ UMC_VENDOR_ID,	CPU_VENDOR_UMC },	/* UMC UMC UMC  */
+	{ NEXGEN_VENDOR_ID,	CPU_VENDOR_NEXGEN },	/* NexGenDriven */
+	{ RISE_VENDOR_ID,	CPU_VENDOR_RISE },	/* RiseRiseRise */
+#if 0
+	/* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
+	{ "TransmetaCPU",	CPU_VENDOR_TRANSMETA },
+#endif
+#endif
+};
+
+void
+printcpuinfo(void)
+{
+	u_int regs[4], i;
+	char *brand;
+
+	cpu_class = cpus[cpu].cpu_class;
+	printf("CPU: ");
+	strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
+
+	/* Check for extended CPUID information and a processor name. */
+	if (cpu_exthigh >= 0x80000004) {
+		brand = cpu_brand;
+		for (i = 0x80000002; i < 0x80000005; i++) {
+			do_cpuid(i, regs);
+			memcpy(brand, regs, sizeof(regs));
+			brand += sizeof(regs);
+		}
+	}
+
+	switch (cpu_vendor_id) {
+	case CPU_VENDOR_INTEL:
+#ifdef __i386__
+		if ((cpu_id & 0xf00) > 0x300) {
+			u_int brand_index;
+
+			cpu_model[0] = '\0';
+
+			switch (cpu_id & 0x3000) {
+			case 0x1000:
+				strcpy(cpu_model, "Overdrive ");
+				break;
+			case 0x2000:
+				strcpy(cpu_model, "Dual ");
+				break;
+			}
+
+			switch (cpu_id & 0xf00) {
+			case 0x400:
+				strcat(cpu_model, "i486 ");
+			        /* Check the particular flavor of 486 */
+				switch (cpu_id & 0xf0) {
+				case 0x00:
+				case 0x10:
+					strcat(cpu_model, "DX");
+					break;
+				case 0x20:
+					strcat(cpu_model, "SX");
+					break;
+				case 0x30:
+					strcat(cpu_model, "DX2");
+					break;
+				case 0x40:
+					strcat(cpu_model, "SL");
+					break;
+				case 0x50:
+					strcat(cpu_model, "SX2");
+					break;
+				case 0x70:
+					strcat(cpu_model,
+					    "DX2 Write-Back Enhanced");
+					break;
+				case 0x80:
+					strcat(cpu_model, "DX4");
+					break;
+				}
+				break;
+			case 0x500:
+			        /* Check the particular flavor of 586 */
+			        strcat(cpu_model, "Pentium");
+			        switch (cpu_id & 0xf0) {
+				case 0x00:
+				        strcat(cpu_model, " A-step");
+					break;
+				case 0x10:
+				        strcat(cpu_model, "/P5");
+					break;
+				case 0x20:
+				        strcat(cpu_model, "/P54C");
+					break;
+				case 0x30:
+				        strcat(cpu_model, "/P24T");
+					break;
+				case 0x40:
+				        strcat(cpu_model, "/P55C");
+					break;
+				case 0x70:
+				        strcat(cpu_model, "/P54C");
+					break;
+				case 0x80:
+				        strcat(cpu_model, "/P55C (quarter-micron)");
+					break;
+				default:
+				        /* nothing */
+					break;
+				}
+#if defined(I586_CPU) && !defined(NO_F00F_HACK)
+				/*
+				 * XXX - If/when Intel fixes the bug, this
+				 * should also check the version of the
+				 * CPU, not just that it's a Pentium.
+				 */
+				has_f00f_bug = 1;
+#endif
+				break;
+			case 0x600:
+			        /* Check the particular flavor of 686 */
+  			        switch (cpu_id & 0xf0) {
+				case 0x00:
+				        strcat(cpu_model, "Pentium Pro A-step");
+					break;
+				case 0x10:
+				        strcat(cpu_model, "Pentium Pro");
+					break;
+				case 0x30:
+				case 0x50:
+				case 0x60:
+				        strcat(cpu_model,
+				"Pentium II/Pentium II Xeon/Celeron");
+					cpu = CPU_PII;
+					break;
+				case 0x70:
+				case 0x80:
+				case 0xa0:
+				case 0xb0:
+				        strcat(cpu_model,
+					"Pentium III/Pentium III Xeon/Celeron");
+					cpu = CPU_PIII;
+					break;
+				default:
+				        strcat(cpu_model, "Unknown 80686");
+					break;
+				}
+				break;
+			case 0xf00:
+				strcat(cpu_model, "Pentium 4");
+				cpu = CPU_P4;
+				break;
+			default:
+				strcat(cpu_model, "unknown");
+				break;
+			}
+
+			/*
+			 * If we didn't get a brand name from the extended
+			 * CPUID, try to look it up in the brand table.
+			 */
+			if (cpu_high > 0 && *cpu_brand == '\0') {
+				brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
+				if (brand_index <= MAX_BRAND_INDEX &&
+				    cpu_brandtable[brand_index] != NULL)
+					strcpy(cpu_brand,
+					    cpu_brandtable[brand_index]);
+			}
+		}
+#else
+		/* Please make up your mind folks! */
+		strcat(cpu_model, "EM64T");
+#endif
+		break;
+	case CPU_VENDOR_AMD:
+		/*
+		 * Values taken from AMD Processor Recognition
+		 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
+		 * (also describes ``Features'' encodings.
+		 */
+		strcpy(cpu_model, "AMD ");
+#ifdef __i386__
+		switch (cpu_id & 0xFF0) {
+		case 0x410:
+			strcat(cpu_model, "Standard Am486DX");
+			break;
+		case 0x430:
+			strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
+			break;
+		case 0x470:
+			strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
+			break;
+		case 0x480:
+			strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
+			break;
+		case 0x490:
+			strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
+			break;
+		case 0x4E0:
+			strcat(cpu_model, "Am5x86 Write-Through");
+			break;
+		case 0x4F0:
+			strcat(cpu_model, "Am5x86 Write-Back");
+			break;
+		case 0x500:
+			strcat(cpu_model, "K5 model 0");
+			break;
+		case 0x510:
+			strcat(cpu_model, "K5 model 1");
+			break;
+		case 0x520:
+			strcat(cpu_model, "K5 PR166 (model 2)");
+			break;
+		case 0x530:
+			strcat(cpu_model, "K5 PR200 (model 3)");
+			break;
+		case 0x560:
+			strcat(cpu_model, "K6");
+			break;
+		case 0x570:
+			strcat(cpu_model, "K6 266 (model 1)");
+			break;
+		case 0x580:
+			strcat(cpu_model, "K6-2");
+			break;
+		case 0x590:
+			strcat(cpu_model, "K6-III");
+			break;
+		case 0x5a0:
+			strcat(cpu_model, "Geode LX");
+			/*
+			 * Make sure the TSC runs through suspension,
+			 * otherwise we can't use it as timecounter
+			 */
+			wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
+			break;
+		default:
+			strcat(cpu_model, "Unknown");
+			break;
+		}
+#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
+		if ((cpu_id & 0xf00) == 0x500) {
+			if (((cpu_id & 0x0f0) > 0)
+			    && ((cpu_id & 0x0f0) < 0x60)
+			    && ((cpu_id & 0x00f) > 3))
+				enable_K5_wt_alloc();
+			else if (((cpu_id & 0x0f0) > 0x80)
+				 || (((cpu_id & 0x0f0) == 0x80)
+				     && (cpu_id & 0x00f) > 0x07))
+				enable_K6_2_wt_alloc();
+			else if ((cpu_id & 0x0f0) > 0x50)
+				enable_K6_wt_alloc();
+		}
+#endif
+#else
+		if ((cpu_id & 0xf00) == 0xf00)
+			strcat(cpu_model, "AMD64 Processor");
+		else
+			strcat(cpu_model, "Unknown");
+#endif
+		break;
+#ifdef __i386__
+	case CPU_VENDOR_CYRIX:
+		strcpy(cpu_model, "Cyrix ");
+		switch (cpu_id & 0xff0) {
+		case 0x440:
+			strcat(cpu_model, "MediaGX");
+			break;
+		case 0x520:
+			strcat(cpu_model, "6x86");
+			break;
+		case 0x540:
+			cpu_class = CPUCLASS_586;
+			strcat(cpu_model, "GXm");
+			break;
+		case 0x600:
+			strcat(cpu_model, "6x86MX");
+			break;
+		default:
+			/*
+			 * Even though CPU supports the cpuid
+			 * instruction, it can be disabled.
+			 * Therefore, this routine supports all Cyrix
+			 * CPUs.
+			 */
+			switch (cyrix_did & 0xf0) {
+			case 0x00:
+				switch (cyrix_did & 0x0f) {
+				case 0x00:
+					strcat(cpu_model, "486SLC");
+					break;
+				case 0x01:
+					strcat(cpu_model, "486DLC");
+					break;
+				case 0x02:
+					strcat(cpu_model, "486SLC2");
+					break;
+				case 0x03:
+					strcat(cpu_model, "486DLC2");
+					break;
+				case 0x04:
+					strcat(cpu_model, "486SRx");
+					break;
+				case 0x05:
+					strcat(cpu_model, "486DRx");
+					break;
+				case 0x06:
+					strcat(cpu_model, "486SRx2");
+					break;
+				case 0x07:
+					strcat(cpu_model, "486DRx2");
+					break;
+				case 0x08:
+					strcat(cpu_model, "486SRu");
+					break;
+				case 0x09:
+					strcat(cpu_model, "486DRu");
+					break;
+				case 0x0a:
+					strcat(cpu_model, "486SRu2");
+					break;
+				case 0x0b:
+					strcat(cpu_model, "486DRu2");
+					break;
+				default:
+					strcat(cpu_model, "Unknown");
+					break;
+				}
+				break;
+			case 0x10:
+				switch (cyrix_did & 0x0f) {
+				case 0x00:
+					strcat(cpu_model, "486S");
+					break;
+				case 0x01:
+					strcat(cpu_model, "486S2");
+					break;
+				case 0x02:
+					strcat(cpu_model, "486Se");
+					break;
+				case 0x03:
+					strcat(cpu_model, "486S2e");
+					break;
+				case 0x0a:
+					strcat(cpu_model, "486DX");
+					break;
+				case 0x0b:
+					strcat(cpu_model, "486DX2");
+					break;
+				case 0x0f:
+					strcat(cpu_model, "486DX4");
+					break;
+				default:
+					strcat(cpu_model, "Unknown");
+					break;
+				}
+				break;
+			case 0x20:
+				if ((cyrix_did & 0x0f) < 8)
+					strcat(cpu_model, "6x86");	/* Where did you get it? */
+				else
+					strcat(cpu_model, "5x86");
+				break;
+			case 0x30:
+				strcat(cpu_model, "6x86");
+				break;
+			case 0x40:
+				if ((cyrix_did & 0xf000) == 0x3000) {
+					cpu_class = CPUCLASS_586;
+					strcat(cpu_model, "GXm");
+				} else
+					strcat(cpu_model, "MediaGX");
+				break;
+			case 0x50:
+				strcat(cpu_model, "6x86MX");
+				break;
+			case 0xf0:
+				switch (cyrix_did & 0x0f) {
+				case 0x0d:
+					strcat(cpu_model, "Overdrive CPU");
+					break;
+				case 0x0e:
+					strcpy(cpu_model, "Texas Instruments 486SXL");
+					break;
+				case 0x0f:
+					strcat(cpu_model, "486SLC/DLC");
+					break;
+				default:
+					strcat(cpu_model, "Unknown");
+					break;
+				}
+				break;
+			default:
+				strcat(cpu_model, "Unknown");
+				break;
+			}
+			break;
+		}
+		break;
+	case CPU_VENDOR_RISE:
+		strcpy(cpu_model, "Rise ");
+		switch (cpu_id & 0xff0) {
+		case 0x500:	/* 6401 and 6441 (Kirin) */
+		case 0x520:	/* 6510 (Lynx) */
+			strcat(cpu_model, "mP6");
+			break;
+		default:
+			strcat(cpu_model, "Unknown");
+		}
+		break;
+#endif
+	case CPU_VENDOR_CENTAUR:
+#ifdef __i386__
+		switch (cpu_id & 0xff0) {
+		case 0x540:
+			strcpy(cpu_model, "IDT WinChip C6");
+			break;
+		case 0x580:
+			strcpy(cpu_model, "IDT WinChip 2");
+			break;
+		case 0x590:
+			strcpy(cpu_model, "IDT WinChip 3");
+			break;
+		case 0x660:
+			strcpy(cpu_model, "VIA C3 Samuel");
+			break;
+		case 0x670:
+			if (cpu_id & 0x8)
+				strcpy(cpu_model, "VIA C3 Ezra");
+			else
+				strcpy(cpu_model, "VIA C3 Samuel 2");
+			break;
+		case 0x680:
+			strcpy(cpu_model, "VIA C3 Ezra-T");
+			break;
+		case 0x690:
+			strcpy(cpu_model, "VIA C3 Nehemiah");
+			break;
+		case 0x6a0:
+		case 0x6d0:
+			strcpy(cpu_model, "VIA C7 Esther");
+			break;
+		case 0x6f0:
+			strcpy(cpu_model, "VIA Nano");
+			break;
+		default:
+			strcpy(cpu_model, "VIA/IDT Unknown");
+		}
+#else
+		strcpy(cpu_model, "VIA ");
+		if ((cpu_id & 0xff0) == 0x6f0)
+			strcat(cpu_model, "Nano Processor");
+		else
+			strcat(cpu_model, "Unknown");
+#endif
+		break;
+#ifdef __i386__
+	case CPU_VENDOR_IBM:
+		strcpy(cpu_model, "Blue Lightning CPU");
+		break;
+	case CPU_VENDOR_NSC:
+		switch (cpu_id & 0xff0) {
+		case 0x540:
+			strcpy(cpu_model, "Geode SC1100");
+			cpu = CPU_GEODE1100;
+			break;
+		default:
+			strcpy(cpu_model, "Geode/NSC unknown");
+			break;
+		}
+		break;
+#endif
+	default:
+		strcat(cpu_model, "Unknown");
+		break;
+	}
+
+	/*
+	 * Replace cpu_model with cpu_brand minus leading spaces if
+	 * we have one.
+	 */
+	brand = cpu_brand;
+	while (*brand == ' ')
+		++brand;
+	if (*brand != '\0')
+		strcpy(cpu_model, brand);
+
+	printf("%s (", cpu_model);
+	if (tsc_freq != 0) {
+		hw_clockrate = (tsc_freq + 5000) / 1000000;
+		printf("%jd.%02d-MHz ",
+		    (intmax_t)(tsc_freq + 4999) / 1000000,
+		    (u_int)((tsc_freq + 4999) / 10000) % 100);
+	}
+	switch(cpu_class) {
+#ifdef __i386__
+	case CPUCLASS_286:
+		printf("286");
+		break;
+	case CPUCLASS_386:
+		printf("386");
+		break;
+#if defined(I486_CPU)
+	case CPUCLASS_486:
+		printf("486");
+		break;
+#endif
+#if defined(I586_CPU)
+	case CPUCLASS_586:
+		printf("586");
+		break;
+#endif
+#if defined(I686_CPU)
+	case CPUCLASS_686:
+		printf("686");
+		break;
+#endif
+#else
+	case CPUCLASS_K8:
+		printf("K8");
+		break;
+#endif
+	default:
+		printf("Unknown");	/* will panic below... */
+	}
+	printf("-class CPU)\n");
+	if (*cpu_vendor)
+		printf("  Origin=\"%s\"", cpu_vendor);
+	if (cpu_id)
+		printf("  Id=0x%x", cpu_id);
+
+	if (cpu_vendor_id == CPU_VENDOR_INTEL ||
+	    cpu_vendor_id == CPU_VENDOR_AMD ||
+	    cpu_vendor_id == CPU_VENDOR_CENTAUR ||
+#ifdef __i386__
+	    cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
+	    cpu_vendor_id == CPU_VENDOR_RISE ||
+	    cpu_vendor_id == CPU_VENDOR_NSC ||
+	    (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
+#endif
+	    0) {
+		printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
+		printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
+		printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
+#ifdef __i386__
+		if (cpu_vendor_id == CPU_VENDOR_CYRIX)
+			printf("\n  DIR=0x%04x", cyrix_did);
+#endif
+
+		/*
+		 * AMD CPUID Specification
+		 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
+		 *
+		 * Intel Processor Identification and CPUID Instruction
+		 * http://www.intel.com/assets/pdf/appnote/241618.pdf
+		 */
+		if (cpu_high > 0) {
+
+			/*
+			 * Here we should probably set up flags indicating
+			 * whether or not various features are available.
+			 * The interesting ones are probably VME, PSE, PAE,

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***


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