svn commit: r270864 - in vendor/device-tree/dist: Bindings Bindings/arm Bindings/arm/exynos Bindings/arm/hisilicon Bindings/arm/keystone Bindings/arm/omap Bindings/arm/samsung Bindings/ata Bindings...

Warner Losh imp at FreeBSD.org
Sun Aug 31 04:34:20 UTC 2014 

Author: imp
Date: Sun Aug 31 04:34:12 2014
New Revision: 270864
URL: http://svnweb.freebsd.org/changeset/base/270864

Log:
  Import from rebasing repo at b78b6b80

Modified:
  vendor/device-tree/dist/Bindings/arm/arch_timer.txt
  vendor/device-tree/dist/Bindings/arm/arm-boards
  vendor/device-tree/dist/Bindings/arm/armada-370-xp-pmsu.txt
  vendor/device-tree/dist/Bindings/arm/atmel-pmc.txt
  vendor/device-tree/dist/Bindings/arm/coherency-fabric.txt
  vendor/device-tree/dist/Bindings/arm/cpus.txt
  vendor/device-tree/dist/Bindings/arm/exynos/power_domain.txt
  vendor/device-tree/dist/Bindings/arm/gic.txt
  vendor/device-tree/dist/Bindings/arm/global_timer.txt
  vendor/device-tree/dist/Bindings/arm/hisilicon/hisilicon.txt
  vendor/device-tree/dist/Bindings/arm/keystone/keystone.txt
  vendor/device-tree/dist/Bindings/arm/l2cc.txt
  vendor/device-tree/dist/Bindings/arm/marvell,berlin.txt
  vendor/device-tree/dist/Bindings/arm/mvebu-system-controller.txt
  vendor/device-tree/dist/Bindings/arm/omap/l3-noc.txt
  vendor/device-tree/dist/Bindings/arm/omap/omap.txt
  vendor/device-tree/dist/Bindings/arm/pmu.txt
  vendor/device-tree/dist/Bindings/arm/psci.txt
  vendor/device-tree/dist/Bindings/arm/samsung/exynos-adc.txt
  vendor/device-tree/dist/Bindings/arm/samsung/sysreg.txt
  vendor/device-tree/dist/Bindings/arm/tegra.txt
  vendor/device-tree/dist/Bindings/arm/topology.txt
  vendor/device-tree/dist/Bindings/arm/vexpress-sysreg.txt
  vendor/device-tree/dist/Bindings/arm/vexpress.txt
  vendor/device-tree/dist/Bindings/arm/xilinx.txt
  vendor/device-tree/dist/Bindings/ata/ahci-platform.txt
  vendor/device-tree/dist/Bindings/ata/exynos-sata.txt
  vendor/device-tree/dist/Bindings/bus/imx-weim.txt
  vendor/device-tree/dist/Bindings/bus/mvebu-mbus.txt
  vendor/device-tree/dist/Bindings/clock/altr_socfpga.txt
  vendor/device-tree/dist/Bindings/clock/at91-clock.txt
  vendor/device-tree/dist/Bindings/clock/axi-clkgen.txt
  vendor/device-tree/dist/Bindings/clock/bcm-kona-clock.txt
  vendor/device-tree/dist/Bindings/clock/clock-bindings.txt
  vendor/device-tree/dist/Bindings/clock/exynos4-clock.txt
  vendor/device-tree/dist/Bindings/clock/exynos5250-clock.txt
  vendor/device-tree/dist/Bindings/clock/exynos5420-clock.txt
  vendor/device-tree/dist/Bindings/clock/exynos5440-clock.txt
  vendor/device-tree/dist/Bindings/clock/fixed-clock.txt
  vendor/device-tree/dist/Bindings/clock/hi3620-clock.txt
  vendor/device-tree/dist/Bindings/clock/imx25-clock.txt
  vendor/device-tree/dist/Bindings/clock/imx27-clock.txt
  vendor/device-tree/dist/Bindings/clock/imx6q-clock.txt
  vendor/device-tree/dist/Bindings/clock/mvebu-core-clock.txt
  vendor/device-tree/dist/Bindings/clock/mvebu-corediv-clock.txt
  vendor/device-tree/dist/Bindings/clock/mvebu-cpu-clock.txt
  vendor/device-tree/dist/Bindings/clock/mvebu-gated-clock.txt
  vendor/device-tree/dist/Bindings/clock/qcom,gcc.txt
  vendor/device-tree/dist/Bindings/clock/qcom,mmcc.txt
  vendor/device-tree/dist/Bindings/clock/renesas,cpg-mstp-clocks.txt
  vendor/device-tree/dist/Bindings/clock/rockchip.txt
  vendor/device-tree/dist/Bindings/clock/sunxi.txt
  vendor/device-tree/dist/Bindings/clock/ti/apll.txt
  vendor/device-tree/dist/Bindings/clock/ti/dpll.txt
  vendor/device-tree/dist/Bindings/clock/ti/gate.txt
  vendor/device-tree/dist/Bindings/clock/ti/interface.txt
  vendor/device-tree/dist/Bindings/clock/zynq-7000.txt
  vendor/device-tree/dist/Bindings/cpufreq/cpufreq-cpu0.txt
  vendor/device-tree/dist/Bindings/dma/dma.txt
  vendor/device-tree/dist/Bindings/dma/fsl-imx-sdma.txt
  vendor/device-tree/dist/Bindings/dma/mmp-dma.txt
  vendor/device-tree/dist/Bindings/dma/ste-dma40.txt
  vendor/device-tree/dist/Bindings/dma/ti-edma.txt
  vendor/device-tree/dist/Bindings/gpio/gpio-davinci.txt
  vendor/device-tree/dist/Bindings/gpio/gpio-mcp23s08.txt
  vendor/device-tree/dist/Bindings/gpio/gpio.txt
  vendor/device-tree/dist/Bindings/gpio/renesas,gpio-rcar.txt
  vendor/device-tree/dist/Bindings/gpu/nvidia,tegra20-host1x.txt
  vendor/device-tree/dist/Bindings/hwmon/ntc_thermistor.txt
  vendor/device-tree/dist/Bindings/i2c/i2c-arb-gpio-challenge.txt
  vendor/device-tree/dist/Bindings/i2c/i2c-at91.txt
  vendor/device-tree/dist/Bindings/i2c/i2c-designware.txt
  vendor/device-tree/dist/Bindings/i2c/i2c-exynos5.txt
  vendor/device-tree/dist/Bindings/i2c/i2c-mv64xxx.txt
  vendor/device-tree/dist/Bindings/i2c/i2c-rcar.txt
  vendor/device-tree/dist/Bindings/i2c/trivial-devices.txt
  vendor/device-tree/dist/Bindings/iio/magnetometer/hmc5843.txt
  vendor/device-tree/dist/Bindings/interrupt-controller/allwinner,sun4i-ic.txt
  vendor/device-tree/dist/Bindings/interrupt-controller/interrupts.txt
  vendor/device-tree/dist/Bindings/iommu/arm,smmu.txt
  vendor/device-tree/dist/Bindings/leds/leds-gpio.txt
  vendor/device-tree/dist/Bindings/leds/leds-lp55xx.txt
  vendor/device-tree/dist/Bindings/leds/leds-pwm.txt
  vendor/device-tree/dist/Bindings/leds/pca963x.txt
  vendor/device-tree/dist/Bindings/leds/tca6507.txt
  vendor/device-tree/dist/Bindings/media/exynos-jpeg-codec.txt
  vendor/device-tree/dist/Bindings/media/s5p-mfc.txt
  vendor/device-tree/dist/Bindings/media/samsung-fimc.txt
  vendor/device-tree/dist/Bindings/memory-controllers/mvebu-devbus.txt
  vendor/device-tree/dist/Bindings/mfd/arizona.txt
  vendor/device-tree/dist/Bindings/mfd/as3722.txt
  vendor/device-tree/dist/Bindings/mfd/mc13xxx.txt
  vendor/device-tree/dist/Bindings/mfd/omap-usb-host.txt
  vendor/device-tree/dist/Bindings/mfd/omap-usb-tll.txt
  vendor/device-tree/dist/Bindings/mfd/palmas.txt
  vendor/device-tree/dist/Bindings/mfd/s2mps11.txt
  vendor/device-tree/dist/Bindings/mfd/tps65910.txt
  vendor/device-tree/dist/Bindings/mfd/twl4030-power.txt
  vendor/device-tree/dist/Bindings/mfd/twl6040.txt
  vendor/device-tree/dist/Bindings/misc/allwinner,sunxi-sid.txt
  vendor/device-tree/dist/Bindings/misc/atmel-ssc.txt
  vendor/device-tree/dist/Bindings/misc/sram.txt
  vendor/device-tree/dist/Bindings/mmc/exynos-dw-mshc.txt
  vendor/device-tree/dist/Bindings/mmc/k3-dw-mshc.txt
  vendor/device-tree/dist/Bindings/mmc/mmc.txt
  vendor/device-tree/dist/Bindings/mmc/mmci.txt
  vendor/device-tree/dist/Bindings/mmc/samsung-sdhci.txt
  vendor/device-tree/dist/Bindings/mmc/sdhci-pxa.txt
  vendor/device-tree/dist/Bindings/mmc/synopsys-dw-mshc.txt
  vendor/device-tree/dist/Bindings/mmc/ti-omap-hsmmc.txt
  vendor/device-tree/dist/Bindings/mmc/tmio_mmc.txt
  vendor/device-tree/dist/Bindings/mtd/gpmc-nand.txt
  vendor/device-tree/dist/Bindings/mtd/gpmc-nor.txt
  vendor/device-tree/dist/Bindings/mtd/gpmc-onenand.txt
  vendor/device-tree/dist/Bindings/mtd/gpmi-nand.txt
  vendor/device-tree/dist/Bindings/mtd/m25p80.txt
  vendor/device-tree/dist/Bindings/mtd/nand.txt
  vendor/device-tree/dist/Bindings/mtd/pxa3xx-nand.txt
  vendor/device-tree/dist/Bindings/net/allwinner,sun4i-emac.txt
  vendor/device-tree/dist/Bindings/net/arc_emac.txt
  vendor/device-tree/dist/Bindings/net/can/sja1000.txt
  vendor/device-tree/dist/Bindings/net/cavium-mix.txt
  vendor/device-tree/dist/Bindings/net/cavium-pip.txt
  vendor/device-tree/dist/Bindings/net/cdns-emac.txt
  vendor/device-tree/dist/Bindings/net/cpsw-phy-sel.txt
  vendor/device-tree/dist/Bindings/net/cpsw.txt
  vendor/device-tree/dist/Bindings/net/davicom-dm9000.txt
  vendor/device-tree/dist/Bindings/net/davinci-mdio.txt
  vendor/device-tree/dist/Bindings/net/davinci_emac.txt
  vendor/device-tree/dist/Bindings/net/fsl-fec.txt
  vendor/device-tree/dist/Bindings/net/fsl-tsec-phy.txt
  vendor/device-tree/dist/Bindings/net/lpc-eth.txt
  vendor/device-tree/dist/Bindings/net/macb.txt
  vendor/device-tree/dist/Bindings/net/marvell-armada-370-neta.txt
  vendor/device-tree/dist/Bindings/net/marvell-orion-net.txt
  vendor/device-tree/dist/Bindings/net/mdio-gpio.txt
  vendor/device-tree/dist/Bindings/net/micrel-ks8851.txt
  vendor/device-tree/dist/Bindings/net/phy.txt
  vendor/device-tree/dist/Bindings/net/smsc-lan91c111.txt
  vendor/device-tree/dist/Bindings/net/smsc911x.txt
  vendor/device-tree/dist/Bindings/net/stmmac.txt
  vendor/device-tree/dist/Bindings/pci/designware-pcie.txt
  vendor/device-tree/dist/Bindings/pci/nvidia,tegra20-pcie.txt
  vendor/device-tree/dist/Bindings/phy/phy-bindings.txt
  vendor/device-tree/dist/Bindings/phy/samsung-phy.txt
  vendor/device-tree/dist/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/marvell,armada-370-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/marvell,armada-xp-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/marvell,dove-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/marvell,kirkwood-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/marvell,mvebu-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/pinctrl-bindings.txt
  vendor/device-tree/dist/Bindings/pinctrl/pinctrl-single.txt
  vendor/device-tree/dist/Bindings/pinctrl/pinctrl-st.txt
  vendor/device-tree/dist/Bindings/pinctrl/qcom,msm8974-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/renesas,pfc-pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/rockchip,pinctrl.txt
  vendor/device-tree/dist/Bindings/pinctrl/samsung-pinctrl.txt
  vendor/device-tree/dist/Bindings/power_supply/qnap-poweroff.txt
  vendor/device-tree/dist/Bindings/powerpc/4xx/reboot.txt
  vendor/device-tree/dist/Bindings/powerpc/fsl/board.txt
  vendor/device-tree/dist/Bindings/powerpc/fsl/cpus.txt
  vendor/device-tree/dist/Bindings/powerpc/fsl/dcsr.txt
  vendor/device-tree/dist/Bindings/powerpc/fsl/pamu.txt
  vendor/device-tree/dist/Bindings/regulator/act8865-regulator.txt
  vendor/device-tree/dist/Bindings/regulator/gpio-regulator.txt
  vendor/device-tree/dist/Bindings/regulator/palmas-pmic.txt
  vendor/device-tree/dist/Bindings/regulator/pfuze100.txt
  vendor/device-tree/dist/Bindings/regulator/regulator.txt
  vendor/device-tree/dist/Bindings/regulator/s5m8767-regulator.txt
  vendor/device-tree/dist/Bindings/regulator/ti-abb-regulator.txt
  vendor/device-tree/dist/Bindings/regulator/tps65090.txt
  vendor/device-tree/dist/Bindings/rtc/haoyu,hym8563.txt
  vendor/device-tree/dist/Bindings/rtc/sunxi-rtc.txt
  vendor/device-tree/dist/Bindings/serial/atmel-usart.txt
  vendor/device-tree/dist/Bindings/serial/efm32-uart.txt
  vendor/device-tree/dist/Bindings/serial/fsl-lpuart.txt
  vendor/device-tree/dist/Bindings/serial/of-serial.txt
  vendor/device-tree/dist/Bindings/serial/renesas,sci-serial.txt
  vendor/device-tree/dist/Bindings/serial/samsung_uart.txt
  vendor/device-tree/dist/Bindings/serial/snps-dw-apb-uart.txt
  vendor/device-tree/dist/Bindings/sound/ak4104.txt
  vendor/device-tree/dist/Bindings/sound/ak5386.txt
  vendor/device-tree/dist/Bindings/sound/davinci-evm-audio.txt
  vendor/device-tree/dist/Bindings/sound/davinci-mcasp-audio.txt
  vendor/device-tree/dist/Bindings/sound/fsl,esai.txt
  vendor/device-tree/dist/Bindings/sound/fsl,spdif.txt
  vendor/device-tree/dist/Bindings/sound/fsl,ssi.txt
  vendor/device-tree/dist/Bindings/sound/fsl-sai.txt
  vendor/device-tree/dist/Bindings/sound/max98090.txt
  vendor/device-tree/dist/Bindings/sound/mvebu-audio.txt
  vendor/device-tree/dist/Bindings/sound/rt5640.txt
  vendor/device-tree/dist/Bindings/sound/simple-card.txt
  vendor/device-tree/dist/Bindings/sound/ti,tas5086.txt
  vendor/device-tree/dist/Bindings/sound/tlv320aic3x.txt
  vendor/device-tree/dist/Bindings/spi/efm32-spi.txt
  vendor/device-tree/dist/Bindings/spi/fsl-spi.txt
  vendor/device-tree/dist/Bindings/spi/sh-hspi.txt
  vendor/device-tree/dist/Bindings/spi/sh-msiof.txt
  vendor/device-tree/dist/Bindings/spi/spi-bus.txt
  vendor/device-tree/dist/Bindings/spi/spi-davinci.txt
  vendor/device-tree/dist/Bindings/spi/spi-fsl-dspi.txt
  vendor/device-tree/dist/Bindings/spi/spi-samsung.txt
  vendor/device-tree/dist/Bindings/staging/imx-drm/fsl-imx-drm.txt
  vendor/device-tree/dist/Bindings/staging/imx-drm/ldb.txt
  vendor/device-tree/dist/Bindings/thermal/armada-thermal.txt
  vendor/device-tree/dist/Bindings/thermal/exynos-thermal.txt
  vendor/device-tree/dist/Bindings/thermal/rcar-thermal.txt
  vendor/device-tree/dist/Bindings/timer/allwinner,sun4i-timer.txt
  vendor/device-tree/dist/Bindings/timer/allwinner,sun5i-a13-hstimer.txt
  vendor/device-tree/dist/Bindings/usb/atmel-usb.txt
  vendor/device-tree/dist/Bindings/usb/ci-hdrc-imx.txt
  vendor/device-tree/dist/Bindings/usb/dwc2.txt
  vendor/device-tree/dist/Bindings/usb/dwc3.txt
  vendor/device-tree/dist/Bindings/usb/ehci-omap.txt
  vendor/device-tree/dist/Bindings/usb/ehci-orion.txt
  vendor/device-tree/dist/Bindings/usb/exynos-usb.txt
  vendor/device-tree/dist/Bindings/usb/fsl-usb.txt
  vendor/device-tree/dist/Bindings/usb/gr-udc.txt
  vendor/device-tree/dist/Bindings/usb/msm-hsusb.txt
  vendor/device-tree/dist/Bindings/usb/mxs-phy.txt
  vendor/device-tree/dist/Bindings/usb/nvidia,tegra20-usb-phy.txt
  vendor/device-tree/dist/Bindings/usb/ohci-omap3.txt
  vendor/device-tree/dist/Bindings/usb/omap-usb.txt
  vendor/device-tree/dist/Bindings/usb/usb-ehci.txt
  vendor/device-tree/dist/Bindings/usb/usb-xhci.txt
  vendor/device-tree/dist/Bindings/usb/usb3503.txt
  vendor/device-tree/dist/Bindings/vendor-prefixes.txt
  vendor/device-tree/dist/Bindings/video/atmel,lcdc.txt
  vendor/device-tree/dist/Bindings/video/exynos_dp.txt
  vendor/device-tree/dist/Bindings/video/exynos_hdmi.txt
  vendor/device-tree/dist/Bindings/video/exynos_mixer.txt
  vendor/device-tree/dist/Bindings/video/fsl,imx-fb.txt
  vendor/device-tree/dist/Bindings/video/samsung-fimd.txt
  vendor/device-tree/dist/Bindings/watchdog/fsl-imx-wdt.txt
  vendor/device-tree/dist/Bindings/watchdog/marvel.txt
  vendor/device-tree/dist/Bindings/watchdog/sunxi-wdt.txt
  vendor/device-tree/dist/include/dt-bindings/clock/exynos4.h
  vendor/device-tree/dist/include/dt-bindings/clock/exynos5250.h
  vendor/device-tree/dist/include/dt-bindings/clock/exynos5420.h
  vendor/device-tree/dist/include/dt-bindings/clock/exynos5440.h
  vendor/device-tree/dist/include/dt-bindings/clock/hi3620-clock.h
  vendor/device-tree/dist/include/dt-bindings/clock/imx6sl-clock.h
  vendor/device-tree/dist/include/dt-bindings/clock/qcom,gcc-msm8960.h
  vendor/device-tree/dist/include/dt-bindings/clock/qcom,gcc-msm8974.h
  vendor/device-tree/dist/include/dt-bindings/clock/qcom,mmcc-msm8960.h
  vendor/device-tree/dist/include/dt-bindings/clock/r8a7790-clock.h
  vendor/device-tree/dist/include/dt-bindings/clock/r8a7791-clock.h
  vendor/device-tree/dist/include/dt-bindings/clock/tegra114-car.h
  vendor/device-tree/dist/include/dt-bindings/clock/tegra124-car.h
  vendor/device-tree/dist/include/dt-bindings/clock/vf610-clock.h
  vendor/device-tree/dist/include/dt-bindings/mfd/as3722.h
  vendor/device-tree/dist/include/dt-bindings/pinctrl/am43xx.h
  vendor/device-tree/dist/include/dt-bindings/pinctrl/dra.h
  vendor/device-tree/dist/include/dt-bindings/pinctrl/omap.h
  vendor/device-tree/dist/include/dt-bindings/reset/qcom,gcc-msm8960.h
  vendor/device-tree/dist/include/dt-bindings/reset/qcom,mmcc-msm8960.h
  vendor/device-tree/dist/src/arc/angel4.dts
  vendor/device-tree/dist/src/arc/nsimosci.dts
  vendor/device-tree/dist/src/arm/aks-cdu.dts
  vendor/device-tree/dist/src/arm/am335x-bone-common.dtsi
  vendor/device-tree/dist/src/arm/am335x-boneblack.dts
  vendor/device-tree/dist/src/arm/am335x-evm.dts
  vendor/device-tree/dist/src/arm/am335x-evmsk.dts
  vendor/device-tree/dist/src/arm/am335x-igep0033.dtsi
  vendor/device-tree/dist/src/arm/am335x-nano.dts
  vendor/device-tree/dist/src/arm/am33xx-clocks.dtsi
  vendor/device-tree/dist/src/arm/am33xx.dtsi
  vendor/device-tree/dist/src/arm/am3517.dtsi
  vendor/device-tree/dist/src/arm/am4372.dtsi
  vendor/device-tree/dist/src/arm/am43x-epos-evm.dts
  vendor/device-tree/dist/src/arm/am43xx-clocks.dtsi
  vendor/device-tree/dist/src/arm/animeo_ip.dts
  vendor/device-tree/dist/src/arm/armada-370-db.dts
  vendor/device-tree/dist/src/arm/armada-370-mirabox.dts
  vendor/device-tree/dist/src/arm/armada-370-netgear-rn102.dts
  vendor/device-tree/dist/src/arm/armada-370-netgear-rn104.dts
  vendor/device-tree/dist/src/arm/armada-370-rd.dts
  vendor/device-tree/dist/src/arm/armada-370-xp.dtsi
  vendor/device-tree/dist/src/arm/armada-370.dtsi
  vendor/device-tree/dist/src/arm/armada-xp-axpwifiap.dts
  vendor/device-tree/dist/src/arm/armada-xp-db.dts
  vendor/device-tree/dist/src/arm/armada-xp-gp.dts
  vendor/device-tree/dist/src/arm/armada-xp-matrix.dts
  vendor/device-tree/dist/src/arm/armada-xp-mv78230.dtsi
  vendor/device-tree/dist/src/arm/armada-xp-mv78260.dtsi
  vendor/device-tree/dist/src/arm/armada-xp-mv78460.dtsi
  vendor/device-tree/dist/src/arm/armada-xp-netgear-rn2120.dts
  vendor/device-tree/dist/src/arm/armada-xp-openblocks-ax3-4.dts
  vendor/device-tree/dist/src/arm/armada-xp.dtsi
  vendor/device-tree/dist/src/arm/at91-ariag25.dts
  vendor/device-tree/dist/src/arm/at91-cosino.dtsi
  vendor/device-tree/dist/src/arm/at91-cosino_mega2560.dts
  vendor/device-tree/dist/src/arm/at91-foxg20.dts
  vendor/device-tree/dist/src/arm/at91-qil_a9260.dts
  vendor/device-tree/dist/src/arm/at91-sama5d3_xplained.dts
  vendor/device-tree/dist/src/arm/at91rm9200.dtsi
  vendor/device-tree/dist/src/arm/at91rm9200ek.dts
  vendor/device-tree/dist/src/arm/at91sam9260.dtsi
  vendor/device-tree/dist/src/arm/at91sam9263.dtsi
  vendor/device-tree/dist/src/arm/at91sam9263ek.dts
  vendor/device-tree/dist/src/arm/at91sam9g20.dtsi
  vendor/device-tree/dist/src/arm/at91sam9g20ek_common.dtsi
  vendor/device-tree/dist/src/arm/at91sam9g45.dtsi
  vendor/device-tree/dist/src/arm/at91sam9m10g45ek.dts
  vendor/device-tree/dist/src/arm/at91sam9n12.dtsi
  vendor/device-tree/dist/src/arm/at91sam9n12ek.dts
  vendor/device-tree/dist/src/arm/at91sam9x5.dtsi
  vendor/device-tree/dist/src/arm/at91sam9x5_macb0.dtsi
  vendor/device-tree/dist/src/arm/at91sam9x5_macb1.dtsi
  vendor/device-tree/dist/src/arm/at91sam9x5_usart3.dtsi
  vendor/device-tree/dist/src/arm/at91sam9x5cm.dtsi
  vendor/device-tree/dist/src/arm/atlas6.dtsi
  vendor/device-tree/dist/src/arm/bcm11351.dtsi
  vendor/device-tree/dist/src/arm/bcm28155-ap.dts
  vendor/device-tree/dist/src/arm/bcm2835.dtsi
  vendor/device-tree/dist/src/arm/berlin2.dtsi
  vendor/device-tree/dist/src/arm/berlin2cd.dtsi
  vendor/device-tree/dist/src/arm/dove-cubox.dts
  vendor/device-tree/dist/src/arm/dove.dtsi
  vendor/device-tree/dist/src/arm/dra7-evm.dts
  vendor/device-tree/dist/src/arm/dra7.dtsi
  vendor/device-tree/dist/src/arm/dra7xx-clocks.dtsi
  vendor/device-tree/dist/src/arm/efm32gg-dk3750.dts
  vendor/device-tree/dist/src/arm/efm32gg.dtsi
  vendor/device-tree/dist/src/arm/emev2.dtsi
  vendor/device-tree/dist/src/arm/ethernut5.dts
  vendor/device-tree/dist/src/arm/evk-pro3.dts
  vendor/device-tree/dist/src/arm/exynos4.dtsi
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  vendor/device-tree/dist/src/mips/xlp_gvp.dts
  vendor/device-tree/dist/src/powerpc/b4860emu.dts
  vendor/device-tree/dist/src/powerpc/fsl/b4420si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/b4420si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/b4860si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/b4860si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/b4si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p2041si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p2041si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p3041si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p3041si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p4080si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p4080si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p5020si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p5020si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p5040si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/p5040si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/qoriq-sec6.0-0.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/t4240si-post.dtsi
  vendor/device-tree/dist/src/powerpc/fsl/t4240si-pre.dtsi
  vendor/device-tree/dist/src/powerpc/mpc5121.dtsi
  vendor/device-tree/dist/src/powerpc/mpc8308_p1m.dts
  vendor/device-tree/dist/src/powerpc/mpc8308rdb.dts
  vendor/device-tree/dist/src/powerpc/t4240emu.dts
  vendor/device-tree/dist/src/powerpc/t4240qds.dts
  vendor/device-tree/dist/src/xtensa/xtfpga-flash-16m.dtsi
  vendor/device-tree/dist/src/xtensa/xtfpga-flash-4m.dtsi
  vendor/device-tree/dist/src/xtensa/xtfpga.dtsi
  vendor/device-tree/dist/testcase-data/tests-interrupts.dtsi
  vendor/device-tree/dist/testcase-data/tests-phandle.dtsi

Modified: vendor/device-tree/dist/Bindings/arm/arch_timer.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/arch_timer.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/arch_timer.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -19,6 +19,9 @@ to deliver its interrupts via SPIs.
 
 - clock-frequency : The frequency of the main counter, in Hz. Optional.
 
+- always-on : a boolean property. If present, the timer is powered through an
+  always-on power domain, therefore it never loses context.
+
 Example:
 
 	timer {

Modified: vendor/device-tree/dist/Bindings/arm/arm-boards
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/arm-boards	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/arm-boards	Sun Aug 31 04:34:12 2014	(r270864)
@@ -86,3 +86,9 @@ Interrupt controllers:
 	compatible = "arm,versatile-sic";
 	interrupt-controller;
 	#interrupt-cells = <1>;
+
+Required nodes:
+
+- core-module: the root node to the Versatile platforms must have
+  a core-module with regs and the compatible strings
+  "arm,core-module-versatile", "syscon"

Modified: vendor/device-tree/dist/Bindings/arm/armada-370-xp-pmsu.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/armada-370-xp-pmsu.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/armada-370-xp-pmsu.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -1,20 +1,21 @@
 Power Management Service Unit(PMSU)
 -----------------------------------
-Available on Marvell SOCs: Armada 370 and Armada XP
+Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP
 
 Required properties:
 
-- compatible: "marvell,armada-370-xp-pmsu"
+- compatible: should be one of:
+  - "marvell,armada-370-pmsu" for Armada 370 or Armada XP
+  - "marvell,armada-380-pmsu" for Armada 38x
+  - "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now
+    deprecated and will be removed
 
-- reg: Should contain PMSU registers location and length. First pair
-  for the per-CPU SW Reset Control registers, second pair for the
-  Power Management Service Unit.
+- reg: Should contain PMSU registers location and length.
 
 Example:
 
-armada-370-xp-pmsu at d0022000 {
-	compatible = "marvell,armada-370-xp-pmsu";
-	reg = <0xd0022100 0x430>,
-	      <0xd0020800 0x20>;
+armada-370-xp-pmsu at 22000 {
+	compatible = "marvell,armada-370-pmsu";
+	reg = <0x22000 0x1000>;
 };
 

Modified: vendor/device-tree/dist/Bindings/arm/atmel-pmc.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/atmel-pmc.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/atmel-pmc.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -1,7 +1,10 @@
 * Power Management Controller (PMC)
 
 Required properties:
-- compatible: Should be "atmel,at91rm9200-pmc"
+- compatible: Should be "atmel,<chip>-pmc".
+	<chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
+	at91sam9x5, sama5d3
+
 - reg: Should contain PMC registers location and length
 
 Examples:

Modified: vendor/device-tree/dist/Bindings/arm/coherency-fabric.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/coherency-fabric.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/coherency-fabric.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -1,16 +1,33 @@
 Coherency fabric
 ----------------
-Available on Marvell SOCs: Armada 370 and Armada XP
+Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP
 
 Required properties:
 
-- compatible: "marvell,coherency-fabric"
+- compatible: the possible values are:
+
+ * "marvell,coherency-fabric", to be used for the coherency fabric of
+   the Armada 370 and Armada XP.
+
+ * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
+   fabric.
+
+ * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
+   fabric.
 
 - reg: Should contain coherency fabric registers location and
-  length. First pair for the coherency fabric registers, second pair
-  for the per-CPU fabric registers registers.
+  length.
+
+ * For "marvell,coherency-fabric", the first pair for the coherency
+   fabric registers, second pair for the per-CPU fabric registers.
 
-Example:
+ * For "marvell,armada-375-coherency-fabric", only one pair is needed
+   for the per-CPU fabric registers.
+
+ * For "marvell,armada-380-coherency-fabric", only one pair is needed
+   for the per-CPU fabric registers.
+
+Examples:
 
 coherency-fabric at d0020200 {
 	compatible = "marvell,coherency-fabric";
@@ -19,3 +36,8 @@ coherency-fabric at d0020200 {
 
 };
 
+coherency-fabric at 21810 {
+	compatible = "marvell,armada-375-coherency-fabric";
+	reg = <0x21810 0x1c>;
+};
+

Modified: vendor/device-tree/dist/Bindings/arm/cpus.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/cpus.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/cpus.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -152,7 +152,9 @@ nodes to be present and contain the prop
 			    "arm,cortex-a7"
 			    "arm,cortex-a8"
 			    "arm,cortex-a9"
+			    "arm,cortex-a12"
 			    "arm,cortex-a15"
+			    "arm,cortex-a17"
 			    "arm,cortex-a53"
 			    "arm,cortex-a57"
 			    "arm,cortex-m0"
@@ -163,6 +165,7 @@ nodes to be present and contain the prop
 			    "arm,cortex-r4"
 			    "arm,cortex-r5"
 			    "arm,cortex-r7"
+			    "brcm,brahma-b15"
 			    "faraday,fa526"
 			    "intel,sa110"
 			    "intel,sa1100"
@@ -178,9 +181,20 @@ nodes to be present and contain the prop
 		Usage and definition depend on ARM architecture version.
 			# On ARM v8 64-bit this property is required and must
 			  be one of:
-			     "spin-table"
 			     "psci"
-			# On ARM 32-bit systems this property is optional.
+			     "spin-table"
+			# On ARM 32-bit systems this property is optional and
+			  can be one of:
+			    "allwinner,sun6i-a31"
+			    "arm,psci"
+			    "brcm,brahma-b15"
+			    "marvell,armada-375-smp"
+			    "marvell,armada-380-smp"
+			    "marvell,armada-xp-smp"
+			    "qcom,gcc-msm8660"
+			    "qcom,kpss-acc-v1"
+			    "qcom,kpss-acc-v2"
+			    "rockchip,rk3066-smp"
 
 	- cpu-release-addr
 		Usage: required for systems that have an "enable-method"
@@ -191,6 +205,21 @@ nodes to be present and contain the prop
 			  property identifying a 64-bit zero-initialised
 			  memory location.
 
+	- qcom,saw
+		Usage: required for systems that have an "enable-method"
+		       property value of "qcom,kpss-acc-v1" or
+		       "qcom,kpss-acc-v2"
+		Value type: <phandle>
+		Definition: Specifies the SAW[1] node associated with this CPU.
+
+	- qcom,acc
+		Usage: required for systems that have an "enable-method"
+		       property value of "qcom,kpss-acc-v1" or
+		       "qcom,kpss-acc-v2"
+		Value type: <phandle>
+		Definition: Specifies the ACC[2] node associated with this CPU.
+
+
 Example 1 (dual-cluster big.LITTLE system 32-bit):
 
 	cpus {
@@ -382,3 +411,7 @@ cpus {
 		cpu-release-addr = <0 0x20000000>;
 	};
 };
+
+--
+[1] arm/msm/qcom,saw2.txt
+[2] arm/msm/qcom,kpss-acc.txt

Modified: vendor/device-tree/dist/Bindings/arm/exynos/power_domain.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/exynos/power_domain.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/exynos/power_domain.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -9,6 +9,18 @@ Required Properties:
 - reg: physical base address of the controller and length of memory mapped
     region.
 
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+	devices in this power domain are set to oscclk before power gating
+	and restored back after powering on a domain. This is required for
+	all domains which are powered on and off and not required for unused
+	domains.
+- clock-names: The following clocks can be specified:
+	- oscclk: Oscillator clock.
+	- pclkN, clkN: Pairs of parent of input clock and input clock to the
+		devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+		are supported currently.
+
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
@@ -19,6 +31,14 @@ Example:
 		reg = <0x10023C00 0x10>;
 	};
 
+	mfc_pd: power-domain at 10044060 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x10044060 0x20>;
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+			<&clock CLK_MOUT_USER_ACLK333>;
+		clock-names = "oscclk", "pclk0", "clk0";
+	};
+
 Example of the node using power domain:
 
 	node {

Modified: vendor/device-tree/dist/Bindings/arm/gic.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/gic.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/gic.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -16,6 +16,7 @@ Main node required properties:
 	"arm,cortex-a9-gic"
 	"arm,cortex-a7-gic"
 	"arm,arm11mp-gic"
+	"brcm,brahma-b15-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.
@@ -50,6 +51,11 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+		  connected from the peripherals, but are routed dynamically
+		  by a crossbar/multiplexer preceding the GIC. The GIC irq
+		  input line is assigned dynamically when the corresponding
+		  peripheral's crossbar line is mapped.
 Example:
 
 	intc: interrupt-controller at fff11000 {
@@ -57,6 +63,7 @@ Example:
 		#interrupt-cells = <3>;
 		#address-cells = <1>;
 		interrupt-controller;
+		arm,routable-irqs = <160>;
 		reg = <0xfff11000 0x1000>,
 		      <0xfff10100 0x100>;
 	};

Modified: vendor/device-tree/dist/Bindings/arm/global_timer.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/global_timer.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/global_timer.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -4,8 +4,11 @@
 
 ** Timer node required properties:
 
-- compatible : Should be "arm,cortex-a9-global-timer"
-		Driver supports versions r2p0 and above.
+- compatible : should contain
+	     * "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
+	     * "arm,cortex-a9-global-timer" for Cortex-A9 global
+	         timers or any compatible implementation. Note: driver
+	         supports versions r2p0 and above.
 
 - interrupts : One interrupt to each core
 

Modified: vendor/device-tree/dist/Bindings/arm/hisilicon/hisilicon.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/hisilicon/hisilicon.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/hisilicon/hisilicon.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -30,3 +30,28 @@ Example:
 		resume-offset = <0x308>;
 		reboot-offset = <0x4>;
 	};
+
+-----------------------------------------------------------------------
+Hisilicon CPU controller
+
+Required properties:
+- compatible : "hisilicon,cpuctrl"
+- reg : Register address and size
+
+The clock registers and power registers of secondary cores are defined
+in CPU controller, especially in HIX5HD2 SoC.
+
+-----------------------------------------------------------------------
+PCTRL: Peripheral misc control register
+
+Required Properties:
+- compatible: "hisilicon,pctrl"
+- reg: Address and size of pctrl.
+
+Example:
+
+	/* for Hi3620 */
+	pctrl: pctrl at fca09000 {
+		compatible = "hisilicon,pctrl";
+		reg = <0xfca09000 0x1000>;
+	};

Modified: vendor/device-tree/dist/Bindings/arm/keystone/keystone.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/keystone/keystone.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/keystone/keystone.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -8,3 +8,13 @@ Required properties:
  - compatible: All TI specific devices present in Keystone SOC should be in
    the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
    type UART should use the specified compatible for those devices.
+
+Boards:
+-  Keystone 2 Hawking/Kepler EVM
+   compatible = "ti,k2hk-evm","ti,keystone"
+
+-  Keystone 2 Lamarr EVM
+   compatible = "ti,k2l-evm","ti,keystone"
+
+-  Keystone 2 Edison EVM
+   compatible = "ti,k2e-evm","ti,keystone"

Modified: vendor/device-tree/dist/Bindings/arm/l2cc.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/l2cc.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/l2cc.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -40,6 +40,9 @@ Optional properties:
 - arm,filter-ranges : <start length> Starting address and length of window to
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
 - interrupts : 1 combined interrupt.
 - cache-id-part: cache id part number to be used if it is not present
   on hardware

Modified: vendor/device-tree/dist/Bindings/arm/marvell,berlin.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/marvell,berlin.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/marvell,berlin.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -12,6 +12,7 @@ SoC and board used. Currently known SoC 
     "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
     "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
     "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
+    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)
     "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
 
 * Example:
@@ -22,3 +23,120 @@ SoC and board used. Currently known SoC 
 
 	...
 }
+
+* Marvell Berlin CPU control bindings
+
+CPU control register allows various operations on CPUs, like resetting them
+independently.
+
+Required properties:
+- compatible: should be "marvell,berlin-cpu-ctrl"
+- reg: address and length of the register set
+
+Example:
+
+cpu-ctrl at f7dd0000 {
+	compatible = "marvell,berlin-cpu-ctrl";
+	reg = <0xf7dd0000 0x10000>;
+};
+
+* Marvell Berlin2 chip control binding
+
+Marvell Berlin SoCs have a chip control register set providing several
+individual registers dealing with pinmux, padmux, clock, reset, and secondary
+CPU boot address. Unfortunately, the individual registers are spread among the
+chip control registers, so there should be a single DT node only providing the
+different functions which are described below.
+
+Required properties:
+- compatible: shall be one of
+	"marvell,berlin2-chip-ctrl" for BG2
+	"marvell,berlin2cd-chip-ctrl" for BG2CD
+	"marvell,berlin2q-chip-ctrl" for BG2Q
+- reg: address and length of following register sets for
+  BG2/BG2CD: chip control register set
+  BG2Q: chip control register set and cpu pll registers
+
+* Marvell Berlin2 system control binding
+
+Marvell Berlin SoCs have a system control register set providing several
+individual registers dealing with pinmux, padmux, and reset.
+
+Required properties:
+- compatible: should be one of
+	"marvell,berlin2-system-ctrl" for BG2
+	"marvell,berlin2cd-system-ctrl" for BG2CD
+	"marvell,berlin2q-system-ctrl" for BG2Q
+- reg: address and length of the system control register set
+
+* Clock provider binding
+
+As clock related registers are spread among the chip control registers, the
+chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
+SoCs share the same IP for PLLs and clocks, with some minor differences in
+features and register layout.
+
+Required properties:
+- #clock-cells: shall be set to 1
+- clocks: clock specifiers referencing the core clock input clocks
+- clock-names: array of strings describing the input clock specifiers above.
+    Allowed clock-names for the reference clocks are
+      "refclk" for the SoCs osciallator input on all SoCs,
+    and SoC-specific input clocks for
+      BG2/BG2CD: "video_ext0" for the external video clock input
+
+Clocks provided by core clocks shall be referenced by a clock specifier
+indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
+for the corresponding index mapping.
+
+* Pin controller binding
+
+Pin control registers are part of both register sets, chip control and system
+control. The pins controlled are organized in groups, so no actual pin
+information is needed.
+
+A pin-controller node should contain subnodes representing the pin group
+configurations, one per function. Each subnode has the group name and the muxing
+function used.
+
+Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
+a 'function' in the pin-controller subsystem.
+
+Required subnode-properties:
+- groups: a list of strings describing the group names.
+- function: a string describing the function used to mux the groups.
+
+Example:
+
+chip: chip-control at ea0000 {
+	compatible = "marvell,berlin2-chip-ctrl";
+	#clock-cells = <1>;
+	reg = <0xea0000 0x400>;
+	clocks = <&refclk>, <&externaldev 0>;
+	clock-names = "refclk", "video_ext0";
+
+	spi1_pmux: spi1-pmux {
+		groups = "G0";
+		function = "spi1";
+	};
+};
+
+sysctrl: system-controller at d000 {
+	compatible = "marvell,berlin2-system-ctrl";
+	reg = <0xd000 0x100>;
+
+	uart0_pmux: uart0-pmux {
+		groups = "GSM4";
+		function = "uart0";
+	};
+
+	uart1_pmux: uart1-pmux {
+		groups = "GSM5";
+		function = "uart1";
+	};
+
+	uart2_pmux: uart2-pmux {
+		groups = "GSM3";
+		function = "uart2";
+	};
+};

Modified: vendor/device-tree/dist/Bindings/arm/mvebu-system-controller.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/mvebu-system-controller.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/mvebu-system-controller.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -1,12 +1,13 @@
 MVEBU System Controller
 -----------------------
-MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
 
 Required properties:
 
 - compatible: one of:
 	- "marvell,orion-system-controller"
 	- "marvell,armada-370-xp-system-controller"
+	- "marvell,armada-375-system-controller"
 - reg: Should contain system controller registers location and length.
 
 Example:

Modified: vendor/device-tree/dist/Bindings/arm/omap/l3-noc.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/omap/l3-noc.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/omap/l3-noc.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -6,6 +6,8 @@ provided by Arteris.
 Required properties:
 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
                Should be "ti,omap4-l3-noc" for OMAP4 family
+	       Should be "ti,dra7-l3-noc" for DRA7 family
+               Should be "ti,am4372-l3-noc" for AM43 family
 - reg:	Contains L3 register address range for each noc domain.
 - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
 

Modified: vendor/device-tree/dist/Bindings/arm/omap/omap.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/omap/omap.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/omap/omap.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -80,7 +80,10 @@ SoCs:
   compatible = "ti,omap5432", "ti,omap5"
 
 - DRA742
-  compatible = "ti,dra7xx", "ti,dra7"
+  compatible = "ti,dra742", "ti,dra74", "ti,dra7"
+
+- DRA722
+  compatible = "ti,dra722", "ti,dra72", "ti,dra7"
 
 - AM4372
   compatible = "ti,am4372", "ti,am43"
@@ -99,6 +102,15 @@ Boards:
 - OMAP4 PandaBoard : Low cost community board
   compatible = "ti,omap4-panda", "ti,omap4430"
 
+- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
+  compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
+
+- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN
+  compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
+
+- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen
+  compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
+
 - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
   compatible = "ti,omap3-evm", "ti,omap3"
 
@@ -114,5 +126,14 @@ Boards:
 - AM43x EPOS EVM
   compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
 
-- DRA7 EVM:  Software Developement Board for DRA7XX
-  compatible = "ti,dra7-evm", "ti,dra7"
+- AM437x GP EVM
+  compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
+
+- AM437x SK EVM: AM437x StarterKit Evaluation Module
+  compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
+
+- DRA742 EVM:  Software Development Board for DRA742
+  compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
+
+- DRA722 EVM: Software Development Board for DRA722
+  compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"

Modified: vendor/device-tree/dist/Bindings/arm/pmu.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/pmu.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/pmu.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -8,7 +8,9 @@ Required properties:
 
 - compatible : should be one of
 	"arm,armv8-pmuv3"
+	"arm,cortex-a17-pmu"
 	"arm,cortex-a15-pmu"
+	"arm,cortex-a12-pmu"
 	"arm,cortex-a9-pmu"
 	"arm,cortex-a8-pmu"
 	"arm,cortex-a7-pmu"
@@ -16,7 +18,14 @@ Required properties:
 	"arm,arm11mpcore-pmu"
 	"arm,arm1176-pmu"
 	"arm,arm1136-pmu"
-- interrupts : 1 combined interrupt or 1 per core.
+	"qcom,krait-pmu"
+- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
+               interrupt (PPI) then 1 interrupt should be specified.
+
+Optional properties:
+
+- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
+                     events.
 
 Example:
 

Modified: vendor/device-tree/dist/Bindings/arm/psci.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/psci.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/psci.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -21,7 +21,15 @@ to #0.
 
 Main node required properties:
 
- - compatible    : Must be "arm,psci"
+ - compatible    : should contain at least one of:
+
+				 * "arm,psci" : for implementations complying to PSCI versions prior to
+					0.2. For these cases function IDs must be provided.
+
+				 * "arm,psci-0.2" : for implementations complying to PSCI 0.2. Function
+					IDs are not required and should be ignored by an OS with PSCI 0.2
+					support, but are permitted to be present for compatibility with
+					existing software when "arm,psci" is later in the compatible list.
 
  - method        : The method of calling the PSCI firmware. Permitted
                    values are:
@@ -45,6 +53,8 @@ Main node optional properties:
 
 Example:
 
+Case 1: PSCI v0.1 only.
+
 	psci {
 		compatible	= "arm,psci";
 		method		= "smc";
@@ -53,3 +63,28 @@ Example:
 		cpu_on		= <0x95c10002>;
 		migrate		= <0x95c10003>;
 	};
+
+
+Case 2: PSCI v0.2 only
+
+	psci {
+		compatible	= "arm,psci-0.2";
+		method		= "smc";
+	};
+
+Case 3: PSCI v0.2 and PSCI v0.1.
+
+	A DTB may provide IDs for use by kernels without PSCI 0.2 support,
+	enabling firmware and hypervisors to support existing and new kernels.
+	These IDs will be ignored by kernels with PSCI 0.2 support, which will
+	use the standard PSCI 0.2 IDs exclusively.
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "hvc";
+
+		cpu_on = < arbitrary value >;
+		cpu_off = < arbitrary value >;
+
+		...
+	};

Modified: vendor/device-tree/dist/Bindings/arm/samsung/exynos-adc.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/samsung/exynos-adc.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/samsung/exynos-adc.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -14,14 +14,21 @@ Required properties:
 				for exynos4412/5250 controllers.
 			Must be "samsung,exynos-adc-v2" for
 				future controllers.
+			Must be "samsung,exynos3250-adc" for
+				controllers compatible with ADC of Exynos3250.
 - reg:			Contains ADC register address range (base address and
 			length) and the address of the phy enable register.
 - interrupts: 		Contains the interrupt information for the timer. The
 			format is being dependent on which interrupt controller
 			the Samsung device uses.
 - #io-channel-cells = <1>; As ADC has multiple outputs
-- clocks		From common clock binding: handle to adc clock.
-- clock-names		From common clock binding: Shall be "adc".
+- clocks		From common clock bindings: handles to clocks specified
+			in "clock-names" property, in the same order.
+- clock-names		From common clock bindings: list of clock input names
+			used by ADC block:
+			- "adc" : ADC bus clock
+			- "sclk" : ADC special clock (only for Exynos3250 and
+				   compatible ADC block)
 - vdd-supply		VDD input supply.
 
 Note: child nodes can be added for auto probing from device tree.
@@ -41,6 +48,20 @@ adc: adc at 12D10000 {
 	vdd-supply = <&buck5_reg>;
 };
 
+Example: adding device info in dtsi file for Exynos3250 with additional sclk
+
+adc: adc at 126C0000 {
+	compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
+	reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+	interrupts = <0 137 0>;
+	#io-channel-cells = <1>;
+	io-channel-ranges;
+
+	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+	clock-names = "adc", "sclk";
+
+	vdd-supply = <&buck5_reg>;
+};
 
 Example: Adding child nodes in dts file
 
@@ -48,7 +69,7 @@ adc at 12D10000 {
 
 	/* NTC thermistor is a hwmon device */
 	ncp15wb473 at 0 {
-		compatible = "ntc,ncp15wb473";
+		compatible = "murata,ncp15wb473";
 		pullup-uv = <1800000>;
 		pullup-ohm = <47000>;
 		pulldown-ohm = <0>;

Modified: vendor/device-tree/dist/Bindings/arm/samsung/sysreg.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/samsung/sysreg.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/samsung/sysreg.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -1,8 +1,10 @@
 SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
 
 Properties:
- - compatible : should contain "samsung,<chip name>-sysreg", "syscon";
-   For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
+ - compatible : should contain two values. First value must be one from following list:
+		- "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
+		- "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
+		second value must be always "syscon".
  - reg : offset and length of the register set.
 
 Example:
@@ -10,3 +12,8 @@ Example:
 		compatible = "samsung,exynos4-sysreg", "syscon";
 		reg = <0x10010000 0x400>;
 	};
+
+	syscon at 10050000 {
+		compatible = "samsung,exynos5-sysreg", "syscon";
+		reg = <0x10050000 0x5000>;
+	};

Modified: vendor/device-tree/dist/Bindings/arm/tegra.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/tegra.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/tegra.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -30,6 +30,8 @@ board-specific compatible values:
   nvidia,seaboard
   nvidia,ventana
   nvidia,whistler
+  toradex,apalis_t30
+  toradex,apalis_t30-eval
   toradex,colibri_t20-512
   toradex,iris
 

Modified: vendor/device-tree/dist/Bindings/arm/topology.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/topology.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/topology.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -75,9 +75,10 @@ The cpu-map node can only contain three 
 
 whose bindings are described in paragraph 3.
 
-The nodes describing the CPU topology (cluster/core/thread) can only be
-defined within the cpu-map node.
-Any other configuration is consider invalid and therefore must be ignored.
+The nodes describing the CPU topology (cluster/core/thread) can only
+be defined within the cpu-map node and every core/thread in the system
+must be defined within the topology.  Any other configuration is
+invalid and therefore must be ignored.
 
 ===========================================
 2.1 - cpu-map child nodes naming convention

Modified: vendor/device-tree/dist/Bindings/arm/vexpress-sysreg.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/vexpress-sysreg.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/vexpress-sysreg.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -8,6 +8,8 @@ interrupt generation, MMC and NOR Flash 
 Required node properties:
 - compatible value : = "arm,vexpress,sysreg";
 - reg : physical base address and the size of the registers window
+
+Deprecated properties, replaced by GPIO subnodes (see below):
 - gpio-controller : specifies that the node is a GPIO controller
 - #gpio-cells : size of the GPIO specifier, should be 2:
   - first cell is the pseudo-GPIO line number:
@@ -16,35 +18,86 @@ Required node properties:
     2 - NOR FLASH WPn
   - second cell can take standard GPIO flags (currently ignored).
 
+Control registers providing pseudo-GPIO lines must be represented
+by subnodes, each of them requiring the following properties:
+- compatible value : one of
+			"arm,vexpress-sysreg,sys_led"
+			"arm,vexpress-sysreg,sys_mci"
+			"arm,vexpress-sysreg,sys_flash"
+- gpio-controller : makes the node a GPIO controller
+- #gpio-cells : size of the GPIO specifier, must be 2:
+  - first cell is the function number:
+    - for sys_led : 0..7 = LED 0..7
+    - for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
+    - for sys_flash : 0 = NOR FLASH WPn
+  - second cell can take standard GPIO flags (currently ignored).
+
 Example:
 	v2m_sysreg: sysreg at 10000000 {
  		compatible = "arm,vexpress-sysreg";
  		reg = <0x10000000 0x1000>;
-		gpio-controller;
-		#gpio-cells = <2>;
+
+		v2m_led_gpios: sys_led at 08 {
+			compatible = "arm,vexpress-sysreg,sys_led";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		v2m_mmc_gpios: sys_mci at 48 {
+			compatible = "arm,vexpress-sysreg,sys_mci";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		v2m_flash_gpios: sys_flash at 4c {
+			compatible = "arm,vexpress-sysreg,sys_flash";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
  	};
 
 This block also can also act a bridge to the platform's configuration
 bus via "system control" interface, addressing devices with site number,
 position in the board stack, config controller, function and device
-numbers - see motherboard's TRM for more details.
-
-The node describing a config device must refer to the sysreg node via
-"arm,vexpress,config-bridge" phandle (can be also defined in the node's
-parent) and relies on the board topology properties - see main vexpress
-node documentation for more details. It must also define the following
-property:
-- arm,vexpress-sysreg,func : must contain two cells:
-  - first cell defines function number (eg. 1 for clock generator,
-    2 for voltage regulators etc.)
-  - device number (eg. osc 0, osc 1 etc.)
+numbers - see motherboard's TRM for more details. All configuration
+controller accessible via this interface must reference the sysreg
+node via "arm,vexpress,config-bridge" phandle and define appropriate
+topology properties - see main vexpress node documentation for more
+details. Each child of such node describes one function and must
+define the following properties:
+- compatible value : must be one of (corresponding to the TRM):
+	"arm,vexpress-amp"
+	"arm,vexpress-dvimode"
+	"arm,vexpress-energy"
+	"arm,vexpress-muxfpga"
+	"arm,vexpress-osc"
+	"arm,vexpress-power"
+	"arm,vexpress-reboot"
+	"arm,vexpress-reset"
+	"arm,vexpress-scc"
+	"arm,vexpress-shutdown"
+	"arm,vexpress-temp"
+	"arm,vexpress-volt"
+- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
+  - first cell of each group defines the function number
+    (eg. 1 for clock generator, 2 for voltage regulators etc.)
+  - second cell of each group defines device number (eg. osc 0,
+    osc 1 etc.)
+  - some functions (eg. energy meter, with its 64 bit long counter)
+    are using more than one function/device number pair
 
 Example:
 	mcc {
+		compatible = "arm,vexpress,config-bus";
 		arm,vexpress,config-bridge = <&v2m_sysreg>;
 
 		osc at 0 {
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 0>;
 		};
+
+		energy at 0 {
+			compatible = "arm,vexpress-energy";
+			arm,vexpress-sysreg,func = <13 0>, <13 1>;
+		};
 	};

Modified: vendor/device-tree/dist/Bindings/arm/vexpress.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/vexpress.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/vexpress.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -80,12 +80,17 @@ but also control clock generators, volta
 environmental data like temperature, power consumption etc. Even
 the video output switch (FPGA) is controlled that way.
 
-Nodes describing devices controlled by this infrastructure should
-point at the bridge device node:
+The controllers are not mapped into normal memory address space
+and must be accessed through bridges - other devices capable
+of generating transactions on the configuration bus.
+
+The nodes describing configuration controllers must define
+the following properties:
+- compatible value:
+	compatible = "arm,vexpress,config-bus";
 - bridge phandle:
 	arm,vexpress,config-bridge = <phandle>;
-This property can be also defined in a parent node (eg. for a DCC)
-and is effective for all children.
+and children describing available functions.
 
 
 Platform topology
@@ -197,7 +202,7 @@ Example of a VE tile description (simpli
 	};
 
 	dcc {
-		compatible = "simple-bus";
+		compatible = "arm,vexpress,config-bus";
 		arm,vexpress,config-bridge = <&v2m_sysreg>;
 
 		osc at 0 {

Modified: vendor/device-tree/dist/Bindings/arm/xilinx.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/arm/xilinx.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/arm/xilinx.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -1,7 +1,7 @@
-Xilinx Zynq EP107 Emulation Platform board
+Xilinx Zynq Platforms Device Tree Bindings
 
-This board is an emulation platform for the Zynq product which is
-based on an ARM Cortex A9 processor.
+Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
+shall have the following properties.
 
 Required root node properties:
-    - compatible = "xlnx,zynq-ep107";
+    - compatible = "xlnx,zynq-7000";

Modified: vendor/device-tree/dist/Bindings/ata/ahci-platform.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/ata/ahci-platform.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/ata/ahci-platform.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -3,18 +3,75 @@
 SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
+It is possible, but not required, to represent each port as a sub-node.
+It allows to enable each port independently when dealing with multiple
+PHYs.
+
 Required properties:
-- compatible        : compatible list, contains "snps,spear-ahci"
+- compatible        : compatible string, one of:
+  - "allwinner,sun4i-a10-ahci"
+  - "hisilicon,hisi-ahci"
+  - "ibm,476gtr-ahci"
+  - "marvell,armada-380-ahci"
+  - "snps,dwc-ahci"
+  - "snps,exynos5440-ahci"
+  - "snps,spear-ahci"
+  - "generic-ahci"
 - interrupts        : <interrupt mapping for SATA IRQ>
 - reg               : <registers mapping>
 
+Please note that when using "generic-ahci" you must also specify a SoC specific
+compatible:
+	compatible = "manufacturer,soc-model-ahci", "generic-ahci";
+
 Optional properties:
 - dma-coherent      : Present if dma operations are coherent
+- clocks            : a list of phandle + clock specifier pairs
+- target-supply     : regulator for SATA target power
+- phys              : reference to the SATA PHY node
+- phy-names         : must be "sata-phy"
+
+Required properties when using sub-nodes:
+- #address-cells    : number of cells to encode an address
+- #size-cells       : number of cells representing the size of an address
+
+
+Sub-nodes required properties:
+- reg               : the port number
+- phys              : reference to the SATA PHY node
+
 
-Example:
+Examples:
         sata at ffe08000 {
 		compatible = "snps,spear-ahci";
 		reg = <0xffe08000 0x1000>;
 		interrupts = <115>;
-
         };
+
+	ahci: sata at 01c18000 {
+		compatible = "allwinner,sun4i-a10-ahci";
+		reg = <0x01c18000 0x1000>;
+		interrupts = <56>;
+		clocks = <&pll6 0>, <&ahb_gates 25>;
+		target-supply = <&reg_ahci_5v>;
+	};
+
+With sub-nodes:
+	sata at f7e90000 {
+		compatible = "marvell,berlin2q-achi", "generic-ahci";
+		reg = <0xe90000 0x1000>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&chip CLKID_SATA>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sata0: sata-port at 0 {
+			reg = <0>;
+			phys = <&sata_phy 0>;
+		};
+
+		sata1: sata-port at 1 {
+			reg = <1>;
+			phys = <&sata_phy 1>;
+		};
+	};

Modified: vendor/device-tree/dist/Bindings/ata/exynos-sata.txt
==============================================================================
--- vendor/device-tree/dist/Bindings/ata/exynos-sata.txt	Sat Aug 30 22:39:15 2014	(r270863)
+++ vendor/device-tree/dist/Bindings/ata/exynos-sata.txt	Sun Aug 31 04:34:12 2014	(r270864)
@@ -4,14 +4,27 @@ SATA nodes are defined to describe on-ch
 Each SATA controller should have its own node.
 
 Required properties:
-- compatible        : compatible list, contains "samsung,exynos5-sata"
-- interrupts        : <interrupt mapping for SATA IRQ>
-- reg               : <registers mapping>
-- samsung,sata-freq : <frequency in MHz>
+- compatible		: compatible list, contains "samsung,exynos5-sata"
+- interrupts		: <interrupt mapping for SATA IRQ>
+- reg			: <registers mapping>
+- samsung,sata-freq	: <frequency in MHz>
+- phys			: Must contain exactly one entry as specified
+			  in phy-bindings.txt
+- phy-names		: Must be "sata-phy"
+
+Optional properties:
+- clocks		: Must contain an entry for each entry in clock-names.
+- clock-names		: Shall be "sata" for the external SATA bus clock,
+			  and "sclk_sata" for the internal controller clock.
 
 Example:
-        sata at ffe08000 {
-                compatible = "samsung,exynos5-sata";
-                reg = <0xffe08000 0x1000>;
-                interrupts = <115>;

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***

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