svn commit: r256573 - head/sys/mips/atheros

[Adrian Chadd]

Author: adrian
Date: Wed Oct 16 02:46:00 2013
New Revision: 256573
URL: http://svnweb.freebsd.org/changeset/base/256573

Log:
  Add in a write barrier after each if_arge write.
  
  Without correct barriers, this code just plain doesn't work on the
  mips74k cores (specifically the AR9344.)
  
  In particular, the MDIO register accesses need this barriering or MII bus
  access results in out-of-order garbage.
  
  Tested:
  
  * AR9344 (mips74k)
  * AR9331 (mips24k)

Modified:
  head/sys/mips/atheros/if_argevar.h

Modified: head/sys/mips/atheros/if_argevar.h
==============================================================================
--- head/sys/mips/atheros/if_argevar.h	Wed Oct 16 02:10:35 2013	(r256572)
+++ head/sys/mips/atheros/if_argevar.h	Wed Oct 16 02:46:00 2013	(r256573)
@@ -55,10 +55,17 @@
 /*
  * register space access macros
  */
+#define	ARGE_BARRIER_READ(sc)	bus_barrier(sc->arge_res, 0, 0, \
+				    BUS_SPACE_BARRIER_READ)
+#define	ARGE_BARRIER_WRITE(sc)	bus_barrier(sc->arge_res, 0, 0, \
+				    BUS_SPACE_BARRIER_WRITE)
+#define	ARGE_BARRIER_RW(sc)	bus_barrier(sc->arge_res, 0, 0, \
+				    BUS_SPACE_BARRIER_READ | \
+				    BUS_SPACE_BARRIER_WRITE)
 #define ARGE_WRITE(sc, reg, val)	do {	\
 		bus_write_4(sc->arge_res, (reg), (val)); \
+		ARGE_BARRIER_WRITE((sc)); \
 	} while (0)
-
 #define ARGE_READ(sc, reg)	 bus_read_4(sc->arge_res, (reg))
 
 #define ARGE_SET_BITS(sc, reg, bits)	\
@@ -71,6 +78,9 @@
 	ARGE_WRITE((_sc), (_reg), (_val))
 #define ARGE_MDIO_READ(_sc, _reg)	\
 	ARGE_READ((_sc), (_reg))
+#define	ARGE_MDIO_BARRIER_READ(_sc)	ARGE_BARRIER_READ(_sc)
+#define	ARGE_MDIO_BARRIER_WRITE(_sc)	ARGE_BARRIER_WRITE(_sc)
+#define	ARGE_MDIO_BARRIER_RW(_sc)	ARGE_BARRIER_READ_RW(_sc)
 
 #define ARGE_DESC_EMPTY		(1 << 31)
 #define ARGE_DESC_MORE		(1 << 24)