svn commit: r248781 - head/sys/mips/atheros

[Adrian Chadd]

Author: adrian
Date: Wed Mar 27 03:33:19 2013
New Revision: 248781
URL: http://svnweb.freebsd.org/changeset/base/248781

Log:
  Add the reference clock for each supported chip.
  
  Obtained from:	Linux (openwrt)

Modified:
  head/sys/mips/atheros/ar71xx_chip.c
  head/sys/mips/atheros/ar71xx_cpudef.h
  head/sys/mips/atheros/ar724x_chip.c
  head/sys/mips/atheros/ar91xx_chip.c

Modified: head/sys/mips/atheros/ar71xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_chip.c	Wed Mar 27 00:37:00 2013	(r248780)
+++ head/sys/mips/atheros/ar71xx_chip.c	Wed Mar 27 03:33:19 2013	(r248781)
@@ -78,6 +78,7 @@ __FBSDID("$FreeBSD$");
 uint32_t u_ar71xx_cpu_freq;
 uint32_t u_ar71xx_ahb_freq;
 uint32_t u_ar71xx_ddr_freq;
+uint32_t u_ar71xx_refclk;
 
 static void
 ar71xx_chip_detect_mem_size(void)
@@ -91,6 +92,8 @@ ar71xx_chip_detect_sys_frequency(void)
 	uint32_t freq;
 	uint32_t div;
 
+	u_ar71xx_refclk = AR71XX_BASE_FREQ;
+
 	pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
 
 	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;

Modified: head/sys/mips/atheros/ar71xx_cpudef.h
==============================================================================
--- head/sys/mips/atheros/ar71xx_cpudef.h	Wed Mar 27 00:37:00 2013	(r248780)
+++ head/sys/mips/atheros/ar71xx_cpudef.h	Wed Mar 27 03:33:19 2013	(r248781)
@@ -117,10 +117,12 @@ static inline void ar71xx_device_ddr_flu
 }
 
 /* XXX shouldn't be here! */
+extern uint32_t u_ar71xx_refclk;
 extern uint32_t u_ar71xx_cpu_freq;
 extern uint32_t u_ar71xx_ahb_freq;
 extern uint32_t u_ar71xx_ddr_freq;
 
+static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
 static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
 static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
 static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }

Modified: head/sys/mips/atheros/ar724x_chip.c
==============================================================================
--- head/sys/mips/atheros/ar724x_chip.c	Wed Mar 27 00:37:00 2013	(r248780)
+++ head/sys/mips/atheros/ar724x_chip.c	Wed Mar 27 03:33:19 2013	(r248781)
@@ -73,6 +73,8 @@ ar724x_chip_detect_sys_frequency(void)
 	uint32_t freq;
 	uint32_t div;
 
+	u_ar71xx_refclk = AR724X_BASE_FREQ;
+
 	pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
 
 	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);

Modified: head/sys/mips/atheros/ar91xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar91xx_chip.c	Wed Mar 27 00:37:00 2013	(r248780)
+++ head/sys/mips/atheros/ar91xx_chip.c	Wed Mar 27 03:33:19 2013	(r248781)
@@ -71,6 +71,8 @@ ar91xx_chip_detect_sys_frequency(void)
 	uint32_t freq;
 	uint32_t div;
 
+	u_ar71xx_refclk = AR91XX_BASE_FREQ;
+
 	pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
 
 	div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);