svn commit: r244914 - in head/sys/arm: arm include ti/omap4

[Andrew Turner]

On Tue, 1 Jan 2013 16:59:15 +1300
Andrew Turner <andrew at fubar.geek.nz> wrote:
> On Mon, 31 Dec 2012 14:18:19 -0800
> Oleksandr Tymoshenko <gonzo at freebsd.org> wrote:
> > I think we can use RTL release field of Cache ID register to
> > determine actual hardware release
> > and act accordingly.
> > 
> > 
> Yes, that appears to be correct, I have committed the known values of
> the RTL release field, from the ARM documentation, in r244919. I can
> have a look at detecting which cache controller we are on and adjust
> our behaviour accordingly but won't have any hardware to test with
> until the end of the week.

I have this untested patch that should only enable the errata when we
detect it is required.

Andrew
-------------- next part --------------
A non-text attachment was scrubbed...
Name: pl310_errata.diff
Type: text/x-patch
Size: 3712 bytes
Desc: not available
URL: <http://lists.freebsd.org/pipermail/svn-src-all/attachments/20130101/779529fb/attachment.bin>