svn commit: r246276 - head/sys/arm/ti/cpsw

Tim Kientzle kientzle at FreeBSD.org
Sun Feb 3 01:08:02 UTC 2013


Author: kientzle
Date: Sun Feb  3 01:08:01 2013
New Revision: 246276
URL: http://svnweb.freebsd.org/changeset/base/246276

Log:
  Another overhaul of the CPSW driver for BeagleBone
  
  Major changes:
    * Finally tracked down the flow control setting that
      seems to have been causing TX stalls and watchdog timeouts
    * RX and TX paths now share a lot more code
    * TX interrupt is no longer used; we instead GC finished
      tx queue entries at the bottom of the start routine.
    * TX start now queues fragmented packets directly; it only
      invokes defrag() for occasional very fragmented packets.
    * "sysctl dev.cpsw" dumps controller statistics and queue counts
    * Host Error Interrupt will give extensive debugging information
      if the controller chokes on the queued data.

Modified:
  head/sys/arm/ti/cpsw/if_cpsw.c
  head/sys/arm/ti/cpsw/if_cpswreg.h
  head/sys/arm/ti/cpsw/if_cpswvar.h

Modified: head/sys/arm/ti/cpsw/if_cpsw.c
==============================================================================
--- head/sys/arm/ti/cpsw/if_cpsw.c	Sun Feb  3 00:19:34 2013	(r246275)
+++ head/sys/arm/ti/cpsw/if_cpsw.c	Sun Feb  3 01:08:01 2013	(r246276)
@@ -25,8 +25,22 @@
  */
 
 /*
- * TI 3 Port Switch Ethernet (CPSW) Driver
- * Found in TI8148, AM335x SoCs
+ * TI Common Platform Ethernet Switch (CPSW) Driver
+ * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs.
+ *
+ * This controller is documented in the AM335x Technical Reference
+ * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM
+ * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM.
+ *
+ * It is basically a single Ethernet port (port 0) wired internally to
+ * a 3-port store-and-forward switch connected to two independent
+ * "sliver" controllers (port 1 and port 2).  You can operate the
+ * controller in a variety of different ways by suitably configuring
+ * the slivers and the Address Lookup Engine (ALE) that routes packets
+ * between the ports.
+ *
+ * This code was developed and tested on a BeagleBone with
+ * an AM335x SoC.
  */
 
 #include <sys/cdefs.h>
@@ -76,44 +90,82 @@ __FBSDID("$FreeBSD$");
 
 #include "miibus_if.h"
 
-static int cpsw_probe(device_t dev);
-static int cpsw_attach(device_t dev);
-static int cpsw_detach(device_t dev);
-static int cpsw_shutdown(device_t dev);
-static int cpsw_suspend(device_t dev);
-static int cpsw_resume(device_t dev);
-
-static int cpsw_miibus_readreg(device_t dev, int phy, int reg);
-static int cpsw_miibus_writereg(device_t dev, int phy, int reg, int value);
-
-static int cpsw_ifmedia_upd(struct ifnet *ifp);
-static void cpsw_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
-
-static void cpsw_init(void *arg);
-static void cpsw_init_locked(void *arg);
-static void cpsw_start(struct ifnet *ifp);
-static void cpsw_start_locked(struct ifnet *ifp);
-static void cpsw_stop_locked(struct cpsw_softc *sc);
-static int cpsw_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
-static int cpsw_init_slot_lists(struct cpsw_softc *sc);
-static void cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot);
-static void cpsw_fill_rx_queue_locked(struct cpsw_softc *sc);
-static void cpsw_tx_watchdog(struct cpsw_softc *sc);
+/* Device probe/attach/detach. */
+static int cpsw_probe(device_t);
+static void cpsw_init_slots(struct cpsw_softc *);
+static int cpsw_attach(device_t);
+static void cpsw_free_slot(struct cpsw_softc *, struct cpsw_slot *);
+static int cpsw_detach(device_t);
+
+/* Device Init/shutdown. */
+static void cpsw_init(void *);
+static void cpsw_init_locked(void *);
+static int cpsw_shutdown(device_t);
+static void cpsw_shutdown_locked(struct cpsw_softc *);
+
+/* Device Suspend/Resume. */
+static int cpsw_suspend(device_t);
+static int cpsw_resume(device_t);
 
-static void cpsw_intr_rx_thresh(void *arg);
+/* Ioctl. */
+static int cpsw_ioctl(struct ifnet *, u_long command, caddr_t data);
+
+static int cpsw_miibus_readreg(device_t, int phy, int reg);
+static int cpsw_miibus_writereg(device_t, int phy, int reg, int value);
+
+/* Send/Receive packets. */
 static void cpsw_intr_rx(void *arg);
-static void cpsw_intr_rx_locked(void *arg);
-static void cpsw_intr_tx(void *arg);
-static void cpsw_intr_tx_locked(void *arg);
-static void cpsw_intr_misc(void *arg);
-
-static void cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry);
-static void cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry);
-static int cpsw_ale_uc_entry_set(struct cpsw_softc *sc, uint8_t port, uint8_t *mac);
-static int cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, uint8_t *mac);
-#ifdef CPSW_DEBUG
-static void cpsw_ale_dump_table(struct cpsw_softc *sc);
-#endif
+static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *);
+static void cpsw_rx_enqueue(struct cpsw_softc *);
+static void cpsw_start(struct ifnet *);
+static void cpsw_tx_enqueue(struct cpsw_softc *);
+static int cpsw_tx_dequeue(struct cpsw_softc *);
+
+/* Misc interrupts and watchdog. */
+static void cpsw_intr_rx_thresh(void *);
+static void cpsw_intr_misc(void *);
+static void cpsw_tick(void *);
+static void cpsw_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int cpsw_ifmedia_upd(struct ifnet *);
+static void cpsw_tx_watchdog(struct cpsw_softc *);
+
+/* ALE support */
+static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t idx, uint32_t *ale_entry);
+static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t idx, uint32_t *ale_entry);
+static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t portmap, uint8_t *mac);
+static int cpsw_ale_update_addresses(struct cpsw_softc *, int purge);
+static void cpsw_ale_dump_table(struct cpsw_softc *);
+
+/* Statistics and sysctls. */
+static void cpsw_add_sysctls(struct cpsw_softc *);
+static void cpsw_stats_collect(struct cpsw_softc *);
+static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS);
+
+/*
+ * Arbitrary limit on number of segments in an mbuf to be transmitted.
+ * Packets with more segments than this will be defragmented before
+ * they are queued.
+ */
+#define CPSW_TXFRAGS 8
+
+
+/*
+ * TODO: The CPSW subsystem (CPSW_SS) can drive two independent PHYs
+ * as separate Ethernet ports.  To properly support this, we should
+ * break this into two separate devices: a CPSW_SS device that owns
+ * the interrupts and actually talks to the CPSW hardware, and a
+ * separate CPSW Ethernet child device for each Ethernet port.  The RX
+ * interrupt, for example, would be part of CPSW_SS; it would receive
+ * a packet, note the input port, and then dispatch it to the child
+ * device's interface queue.  Similarly for transmit.
+ *
+ * It's not clear to me whether the device tree should be restructured
+ * with a cpsw_ss node and two child nodes.  That would allow specifying
+ * MAC addresses for each port, for example, but might be overkill.
+ *
+ * Unfortunately, I don't have hardware right now that supports two
+ * Ethernet ports via CPSW.
+ */
 
 static device_method_t cpsw_methods[] = {
 	/* Device interface */
@@ -137,7 +189,6 @@ static driver_t cpsw_driver = {
 
 static devclass_t cpsw_devclass;
 
-
 DRIVER_MODULE(cpsw, simplebus, cpsw_driver, cpsw_devclass, 0, 0);
 DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0);
 MODULE_DEPEND(cpsw, ether, 1, 1, 1);
@@ -152,40 +203,109 @@ static struct resource_spec res_spec[] =
 	{ -1, 0 }
 };
 
-static struct {
-	driver_intr_t *handler;
-	char * description;
-} cpsw_intrs[CPSW_INTR_COUNT + 1] = {
-	{ cpsw_intr_rx_thresh, "CPSW RX threshold interrupt" },
-	{ cpsw_intr_rx,	"CPSW RX interrupt" },
-	{ cpsw_intr_tx,	"CPSW TX interrupt" },
-	{ cpsw_intr_misc, "CPSW misc interrupt" },
+/* Number of entries here must match size of stats
+ * array in struct cpsw_softc. */
+static struct cpsw_stat {
+	int	reg;
+	char *oid;
+} cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = {
+	{0x00, "GoodRxFrames"},
+	{0x04, "BroadcastRxFrames"},
+	{0x08, "MulticastRxFrames"},
+	{0x0C, "PauseRxFrames"},
+	{0x10, "RxCrcErrors"},
+	{0x14, "RxAlignErrors"},
+	{0x18, "OversizeRxFrames"},
+	{0x1c, "RxJabbers"},
+	{0x20, "ShortRxFrames"},
+	{0x24, "RxFragments"},
+	{0x30, "RxOctets"},
+	{0x34, "GoodTxFrames"},
+	{0x38, "BroadcastTxFrames"},
+	{0x3c, "MulticastTxFrames"},
+	{0x40, "PauseTxFrames"},
+	{0x44, "DeferredTxFrames"},
+	{0x48, "CollisionsTxFrames"},
+	{0x4c, "SingleCollisionTxFrames"},
+	{0x50, "MultipleCollisionTxFrames"},
+	{0x54, "ExcessiveCollisions"},
+	{0x58, "LateCollisions"},
+	{0x5c, "TxUnderrun"},
+	{0x60, "CarrierSenseErrors"},
+	{0x64, "TxOctets"},
+	{0x68, "RxTx64OctetFrames"},
+	{0x6c, "RxTx65to127OctetFrames"},
+	{0x70, "RxTx128to255OctetFrames"},
+	{0x74, "RxTx256to511OctetFrames"},
+	{0x78, "RxTx512to1024OctetFrames"},
+	{0x7c, "RxTx1024upOctetFrames"},
+	{0x80, "NetOctets"},
+	{0x84, "RxStartOfFrameOverruns"},
+	{0x88, "RxMiddleOfFrameOverruns"},
+	{0x8c, "RxDmaOverruns"}
 };
 
-/* Locking macros */
+/*
+ * Basic debug support.
+ */
+
+#define IF_DEBUG(sc)  if (sc->cpsw_if_flags & IFF_DEBUG)
+
+static void
+cpsw_debugf_head(const char *funcname)
+{
+	int t = (int)(time_second % (24 * 60 * 60));
+
+	printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname);
+}
+
+#include <machine/stdarg.h>
+static void
+cpsw_debugf(const char *fmt, ...)
+{
+	va_list ap;
+
+	va_start(ap, fmt);
+	vprintf(fmt, ap);
+	va_end(ap);
+	printf("\n");
+
+}
+
+#define CPSW_DEBUGF(a) do {					\
+	IF_DEBUG(sc) {						\
+		cpsw_debugf_head(__func__);			\
+		cpsw_debugf a;					\
+	}							\
+} while (0)
+
+
+/*
+ * Locking macros
+ */
 #define CPSW_TX_LOCK(sc) do {					\
-		mtx_assert(&(sc)->rx_lock, MA_NOTOWNED);		\
-		mtx_lock(&(sc)->tx_lock);				\
+		mtx_assert(&(sc)->rx.lock, MA_NOTOWNED);		\
+		mtx_lock(&(sc)->tx.lock);				\
 } while (0)
 
-#define CPSW_TX_UNLOCK(sc)	mtx_unlock(&(sc)->tx_lock)
-#define CPSW_TX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->tx_lock, MA_OWNED)
+#define CPSW_TX_UNLOCK(sc)	mtx_unlock(&(sc)->tx.lock)
+#define CPSW_TX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->tx.lock, MA_OWNED)
 
 #define CPSW_RX_LOCK(sc) do {					\
-		mtx_assert(&(sc)->tx_lock, MA_NOTOWNED);		\
-		mtx_lock(&(sc)->rx_lock);				\
+		mtx_assert(&(sc)->tx.lock, MA_NOTOWNED);		\
+		mtx_lock(&(sc)->rx.lock);				\
 } while (0)
 
-#define CPSW_RX_UNLOCK(sc)		mtx_unlock(&(sc)->rx_lock)
-#define CPSW_RX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->rx_lock, MA_OWNED)
+#define CPSW_RX_UNLOCK(sc)		mtx_unlock(&(sc)->rx.lock)
+#define CPSW_RX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->rx.lock, MA_OWNED)
 
 #define CPSW_GLOBAL_LOCK(sc) do {					\
-		if ((mtx_owned(&(sc)->tx_lock) ? 1 : 0) !=	\
-		    (mtx_owned(&(sc)->rx_lock) ? 1 : 0)) {		\
+		if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) !=	\
+		    (mtx_owned(&(sc)->rx.lock) ? 1 : 0)) {		\
 			panic("cpsw deadlock possibility detection!");	\
 		}							\
-		mtx_lock(&(sc)->tx_lock);				\
-		mtx_lock(&(sc)->rx_lock);				\
+		mtx_lock(&(sc)->tx.lock);				\
+		mtx_lock(&(sc)->rx.lock);				\
 } while (0)
 
 #define CPSW_GLOBAL_UNLOCK(sc) do {					\
@@ -198,35 +318,128 @@ static struct {
 		CPSW_RX_LOCK_ASSERT(sc);				\
 } while (0)
 
+/*
+ * Read/Write macros
+ */
+#define	cpsw_read_4(sc, reg)		bus_read_4(sc->res[0], reg)
+#define	cpsw_write_4(sc, reg, val)	bus_write_4(sc->res[0], reg, val)
 
-#include <machine/stdarg.h>
-static void
-cpsw_debugf_head(const char *funcname)
-{
-	int t = (int)(time_second % (24 * 60 * 60));
+#define	cpsw_cpdma_bd_offset(i)	(CPSW_CPPI_RAM_OFFSET + ((i)*16))
 
-	printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname);
+#define	cpsw_cpdma_bd_paddr(sc, slot)				\
+	(slot->bd_offset + vtophys(rman_get_start(sc->res[0])))
+#define	cpsw_cpdma_read_bd(sc, slot, val)				\
+	bus_read_region_4(sc->res[0], slot->bd_offset, (uint32_t *) val, 4)
+#define	cpsw_cpdma_write_bd(sc, slot, val)				\
+	bus_write_region_4(sc->res[0], slot->bd_offset, (uint32_t *) val, 4)
+#define	cpsw_cpdma_write_bd_next(sc, slot, next_slot)			\
+	cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
+#define	cpsw_cpdma_read_bd_flags(sc, slot)		\
+	bus_read_2(sc->res[0], slot->bd_offset + 14)
+#define	cpsw_write_hdp_slot(sc, queue, slot)				\
+	cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
+#define	CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0))
+#define	cpsw_read_cp(sc, queue)				\
+	cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 
+#define	cpsw_write_cp(sc, queue, val)				\
+	cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
+#define	cpsw_write_cp_slot(sc, queue, slot)		\
+	cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot))
+
+#if 0
+/* XXX temporary function versions for debugging. */
+static void
+cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
+{
+	uint32_t reg = queue->hdp_offset;
+	uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
+	CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));
+	cpsw_write_4(sc, reg, v);
 }
 
 static void
-cpsw_debugf(const char *fmt, ...)
+cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
+{
+	uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
+	CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue)));
+	cpsw_write_cp(sc, queue, v);
+}
+#endif
+
+/*
+ * Expanded dump routines for verbose debugging.
+ */
+static void
+cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
 {
-	va_list ap;
+	static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ",
+	    "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun",
+	    "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1",
+	    "Port0"};
+	struct cpsw_cpdma_bd bd;
+	const char *sep;
+	int i;
 
-	va_start(ap, fmt);
-	vprintf(fmt, ap);
-	va_end(ap);
+	cpsw_cpdma_read_bd(sc, slot, &bd);
+	printf("BD Addr: 0x%08x   Next: 0x%08x\n", cpsw_cpdma_bd_paddr(sc, slot), bd.next);
+	printf("  BufPtr: 0x%08x   BufLen: 0x%08x\n", bd.bufptr, bd.buflen);
+	printf("  BufOff: 0x%08x   PktLen: 0x%08x\n", bd.bufoff, bd.pktlen);
+	printf("  Flags: ");
+	sep = "";
+	for (i = 0; i < 16; ++i) {
+		if (bd.flags & (1 << (15 - i))) {
+			printf("%s%s", sep, flags[i]);
+			sep = ",";
+		}
+	}
 	printf("\n");
+	if (slot->mbuf) {
+		printf("  Ether:  %14D\n",
+		    (char *)(slot->mbuf->m_hdr.mh_data), " ");
+		printf("  Packet: %16D\n",
+		    (char *)(slot->mbuf->m_hdr.mh_data) + 14, " ");
+	}
+}
+
+#define CPSW_DUMP_SLOT(cs, slot) do {				\
+	IF_DEBUG(sc) {						\
+		cpsw_dump_slot(sc, slot);			\
+	}							\
+} while (0)
+
 
+static void
+cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
+{
+	struct cpsw_slot *slot;
+	int i = 0;
+	int others = 0;
+
+	STAILQ_FOREACH(slot, q, next) {
+		if (i > 4)
+			++others;
+		else
+			cpsw_dump_slot(sc, slot);
+		++i;
+	}
+	if (others)
+		printf(" ... and %d more.\n", others);
+	printf("\n");
 }
 
-#define CPSW_DEBUGF(a) do {						\
-		if (sc->cpsw_if_flags & IFF_DEBUG) {			\
-			cpsw_debugf_head(__func__);			\
-			cpsw_debugf a;					\
-		}							\
+#define CPSW_DUMP_QUEUE(sc, q) do {				\
+	IF_DEBUG(sc) {						\
+		cpsw_dump_queue(sc, q);				\
+	}							\
 } while (0)
 
+
+/*
+ *
+ * Device Probe, Attach, Detach.
+ *
+ */
+
 static int
 cpsw_probe(device_t dev)
 {
@@ -238,18 +451,107 @@ cpsw_probe(device_t dev)
 	return (BUS_PROBE_DEFAULT);
 }
 
+
+static void
+cpsw_init_slots(struct cpsw_softc *sc)
+{
+	struct cpsw_slot *slot;
+	int i;
+
+	STAILQ_INIT(&sc->avail);
+
+	/* Put the slot descriptors onto the global avail list. */
+	for (i = 0; i < sizeof(sc->_slots) / sizeof(sc->_slots[0]); i++) {
+		slot = &sc->_slots[i];
+		slot->bd_offset = cpsw_cpdma_bd_offset(i);
+		STAILQ_INSERT_TAIL(&sc->avail, slot, next);
+	}
+}
+
+/*
+ * bind an interrupt, add the relevant info to sc->interrupts
+ */
+static int
+cpsw_attach_interrupt(struct cpsw_softc *sc, struct resource *res, driver_intr_t *handler, const char *description)
+{
+	void **pcookie;
+	int error;
+
+	sc->interrupts[sc->interrupt_count].res = res;
+	sc->interrupts[sc->interrupt_count].description = description;
+	pcookie = &sc->interrupts[sc->interrupt_count].ih_cookie;
+
+	error = bus_setup_intr(sc->dev, res, INTR_TYPE_NET | INTR_MPSAFE,
+	    NULL, *handler, sc, pcookie);
+	if (error)
+		device_printf(sc->dev,
+		    "could not setup %s\n", description);
+	else
+		++sc->interrupt_count;
+	return (error);
+}
+
+/*
+ * teardown everything in sc->interrupts.
+ */
+static void
+cpsw_detach_interrupts(struct cpsw_softc *sc)
+{
+	int error;
+	int i;
+
+	for (i = 0; i < sizeof(sc->interrupts) / sizeof(sc->interrupts[0]); ++i) {
+		if (!sc->interrupts[i].ih_cookie)
+			continue;
+		error = bus_teardown_intr(sc->dev,
+		    sc->interrupts[i].res, sc->interrupts[i].ih_cookie);
+		if (error)
+			device_printf(sc->dev, "could not release %s\n",
+			    sc->interrupts[i].description);
+		sc->interrupts[i].ih_cookie = NULL;
+	}
+}
+
+static int
+cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested)
+{
+	const int max_slots = sizeof(sc->_slots) / sizeof(sc->_slots[0]);
+	struct cpsw_slot *slot;
+	int i;
+
+	if (requested < 0)
+		requested = max_slots;
+
+	for (i = 0; i < requested; ++i) {
+		slot = STAILQ_FIRST(&sc->avail);
+		if (slot == NULL)
+			return (0);
+		if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) {
+			if_printf(sc->ifp, "failed to create dmamap\n");
+			return (ENOMEM);
+		}
+		STAILQ_REMOVE_HEAD(&sc->avail, next);
+		STAILQ_INSERT_TAIL(&queue->avail, slot, next);
+		++queue->avail_queue_len;
+		++queue->queue_slots;
+	}
+	return (0);
+}
+
 static int
 cpsw_attach(device_t dev)
 {
+	bus_dma_segment_t segs[1];
 	struct cpsw_softc *sc = device_get_softc(dev);
 	struct mii_softc *miisc;
 	struct ifnet *ifp;
 	void *phy_sc;
-	int i, error, phy;
+	int error, phy, nsegs;
 	uint32_t reg;
 
 	CPSW_DEBUGF((""));
 
+	getbinuptime(&sc->attach_uptime);
 	sc->dev = dev;
 	sc->node = ofw_bus_get_node(dev);
 
@@ -259,10 +561,10 @@ cpsw_attach(device_t dev)
 		return (ENXIO);
 	}
 	/* Initialize mutexes */
-	mtx_init(&sc->tx_lock, device_get_nameunit(dev),
-		"cpsw TX lock", MTX_DEF);
-	mtx_init(&sc->rx_lock, device_get_nameunit(dev),
-		"cpsw RX lock", MTX_DEF);
+	mtx_init(&sc->tx.lock, device_get_nameunit(dev),
+	    "cpsw TX lock", MTX_DEF);
+	mtx_init(&sc->rx.lock, device_get_nameunit(dev),
+	    "cpsw RX lock", MTX_DEF);
 
 	/* Allocate IO and IRQ resources */
 	error = bus_alloc_resources(dev, res_spec, sc->res);
@@ -272,11 +574,11 @@ cpsw_attach(device_t dev)
 		return (ENXIO);
 	}
 
-	reg = cpsw_read_4(CPSW_SS_IDVER);
-	device_printf(dev, "Version %d.%d (%d)\n", (reg >> 8 & 0x7),
+	reg = cpsw_read_4(sc, CPSW_SS_IDVER);
+	device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7),
 		reg & 0xFF, (reg >> 11) & 0x1F);
 
-	//cpsw_add_sysctls(sc); TODO
+	cpsw_add_sysctls(sc);
 
 	/* Allocate a busdma tag and DMA safe memory for mbufs. */
 	error = bus_dma_tag_create(
@@ -285,22 +587,14 @@ cpsw_attach(device_t dev)
 		BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
 		BUS_SPACE_MAXADDR,		/* highaddr */
 		NULL, NULL,			/* filtfunc, filtfuncarg */
-		MCLBYTES, 1,			/* maxsize, nsegments */
+		MCLBYTES, CPSW_TXFRAGS,		/* maxsize, nsegments */
 		MCLBYTES, 0,			/* maxsegsz, flags */
 		NULL, NULL,			/* lockfunc, lockfuncarg */
 		&sc->mbuf_dtag);		/* dmatag */
 	if (error) {
 		device_printf(dev, "bus_dma_tag_create failed\n");
 		cpsw_detach(dev);
-		return (ENOMEM);
-	}
-
-	/* Initialize the tx_avail and rx_avail lists. */
-	error = cpsw_init_slot_lists(sc);
-	if (error) {
-		device_printf(dev, "failed to allocate dmamaps\n");
-		cpsw_detach(dev);
-		return (ENOMEM);
+		return (error);
 	}
 
 	/* Allocate network interface */
@@ -311,6 +605,16 @@ cpsw_attach(device_t dev)
 		return (ENOMEM);
 	}
 
+	/* Allocate the null mbuf and pre-sync it. */
+	sc->null_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+	memset(sc->null_mbuf->m_hdr.mh_data, 0, sc->null_mbuf->m_ext.ext_size);
+	bus_dmamap_create(sc->mbuf_dtag, 0, &sc->null_mbuf_dmamap);
+	bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, sc->null_mbuf_dmamap,
+	    sc->null_mbuf, segs, &nsegs, BUS_DMA_NOWAIT);
+	bus_dmamap_sync(sc->mbuf_dtag, sc->null_mbuf_dmamap,
+	    BUS_DMASYNC_PREWRITE);
+	sc->null_mbuf_paddr = segs[0].ds_addr;
+
 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
@@ -321,11 +625,32 @@ cpsw_attach(device_t dev)
 	ifp->if_start = cpsw_start;
 	ifp->if_ioctl = cpsw_ioctl;
 
-	ifp->if_snd.ifq_drv_maxlen = CPSW_MAX_TX_BUFFERS - 1;
+	cpsw_init_slots(sc);
+
+	/* Allocate slots to TX and RX queues. */
+	STAILQ_INIT(&sc->rx.avail);
+	STAILQ_INIT(&sc->rx.active);
+	STAILQ_INIT(&sc->tx.avail);
+	STAILQ_INIT(&sc->tx.active);
+	// For now:  128 slots to TX, rest to RX.
+	// XXX TODO: start with 32/64 and grow dynamically based on demand.
+	if (cpsw_add_slots(sc, &sc->tx, 128) || cpsw_add_slots(sc, &sc->rx, -1)) {
+		device_printf(dev, "failed to allocate dmamaps\n");
+		cpsw_detach(dev);
+		return (ENOMEM);
+	}
+	device_printf(dev, "Initial queue size TX=%d RX=%d\n",
+	    sc->tx.queue_slots, sc->rx.queue_slots);
+
+	ifp->if_snd.ifq_drv_maxlen = sc->tx.queue_slots;
 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
 	IFQ_SET_READY(&ifp->if_snd);
 
+	sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0);
+	sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0);
+
 	/* Get high part of MAC address from control module (mac_id0_hi) */
+	/* TODO: Get MAC ID1 as well as MAC ID0. */
 	ti_scm_reg_read_4(0x634, &reg);
 	sc->mac_addr[0] = reg & 0xFF;
 	sc->mac_addr[1] = (reg >>  8) & 0xFF;
@@ -338,11 +663,14 @@ cpsw_attach(device_t dev)
 	sc->mac_addr[5] = (reg >>  8) & 0xFF;
 
 	ether_ifattach(ifp, sc->mac_addr);
-	callout_init(&sc->wd_callout, 0);
+	callout_init(&sc->watchdog.callout, 0);
 
 	/* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
 	/* TODO Calculate MDCLK=CLK/(CLKDIV+1) */
-	cpsw_write_4(MDIOCONTROL, 1 << 30 | 1 << 18 | 0xFF);
+	cpsw_write_4(sc, MDIOCONTROL, 1 << 30 | 1 << 18 | 0xFF);
+
+	/* Clear ALE */
+	cpsw_write_4(sc, CPSW_ALE_CONTROL, 1 << 30);
 
 	/* Attach PHY(s) */
 	error = mii_attach(dev, &sc->miibus, ifp, cpsw_ifmedia_upd,
@@ -358,25 +686,38 @@ cpsw_attach(device_t dev)
 	miisc = LIST_FIRST(&sc->mii->mii_phys);
 
 	/* Select PHY and enable interrupts */
-	cpsw_write_4(MDIOUSERPHYSEL0, 1 << 6 | (miisc->mii_phy & 0x1F));
-
-	/* Attach interrupt handlers */
-	for (i = 1; i <= CPSW_INTR_COUNT; ++i) {
-		error = bus_setup_intr(dev, sc->res[i],
-		    INTR_TYPE_NET | INTR_MPSAFE,
-		    NULL, *cpsw_intrs[i - 1].handler,
-		    sc, &sc->ih_cookie[i - 1]);
-		if (error) {
-			device_printf(dev, "could not setup %s\n",
-			    cpsw_intrs[i].description);
-			cpsw_detach(dev);
-			return (error);
-		}
+	cpsw_write_4(sc, MDIOUSERPHYSEL0, 1 << 6 | (miisc->mii_phy & 0x1F));
+	
+	/* Note: We don't use sc->res[3] (TX interrupt) */
+	if (cpsw_attach_interrupt(sc, sc->res[1],
+		cpsw_intr_rx_thresh, "CPSW RX threshold interrupt") ||
+	    cpsw_attach_interrupt(sc, sc->res[2],
+		cpsw_intr_rx, "CPSW RX interrupt") ||
+	    cpsw_attach_interrupt(sc, sc->res[4],
+		cpsw_intr_misc, "CPSW misc interrupt")) {
+		cpsw_detach(dev);
+		return (ENXIO);
 	}
 
 	return (0);
 }
 
+static void
+cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
+{
+	int error;
+
+	if (slot->dmamap) {
+		error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap);
+		KASSERT(error == 0, ("Mapping still active"));
+		slot->dmamap = NULL;
+	}
+	if (slot->mbuf) {
+		m_freem(slot->mbuf);
+		slot->mbuf = NULL;
+	}
+}
+
 static int
 cpsw_detach(device_t dev)
 {
@@ -389,31 +730,20 @@ cpsw_detach(device_t dev)
 	if (device_is_attached(dev)) {
 		ether_ifdetach(sc->ifp);
 		CPSW_GLOBAL_LOCK(sc);
-		cpsw_stop_locked(sc);
+		cpsw_shutdown_locked(sc);
 		CPSW_GLOBAL_UNLOCK(sc);
-		callout_drain(&sc->wd_callout);
+		callout_drain(&sc->watchdog.callout);
 	}
 
 	bus_generic_detach(dev);
 	device_delete_child(dev, sc->miibus);
 
 	/* Stop and release all interrupts */
-	for (i = 0; i < CPSW_INTR_COUNT; ++i) {
-		if (!sc->ih_cookie[i])
-			continue;
-
-		error = bus_teardown_intr(dev, sc->res[1 + i], sc->ih_cookie[i]);
-		if (error)
-			device_printf(dev, "could not release %s\n",
-			    cpsw_intrs[i + 1].description);
-	}
+	cpsw_detach_interrupts(sc);
 
 	/* Free dmamaps and mbufs */
-	for (i = 0; i < CPSW_MAX_TX_BUFFERS; i++) {
-		cpsw_free_slot(sc, &sc->_tx_slots[i]);
-	}
-	for (i = 0; i < CPSW_MAX_RX_BUFFERS; i++) {
-		cpsw_free_slot(sc, &sc->_rx_slots[i]);
+	for (i = 0; i < sizeof(sc->_slots) / sizeof(sc->_slots[0]); ++i) {
+		cpsw_free_slot(sc, &sc->_slots[i]);
 	}
 
 	/* Free DMA tag */
@@ -424,30 +754,181 @@ cpsw_detach(device_t dev)
 	bus_release_resources(dev, res_spec, sc->res);
 
 	/* Destroy mutexes */
-	mtx_destroy(&sc->rx_lock);
-	mtx_destroy(&sc->tx_lock);
+	mtx_destroy(&sc->rx.lock);
+	mtx_destroy(&sc->tx.lock);
 
 	return (0);
 }
 
-static int
-cpsw_suspend(device_t dev)
+/*
+ *
+ * Init/Shutdown.
+ *
+ */
+
+static void
+cpsw_reset(struct cpsw_softc *sc)
 {
-	struct cpsw_softc *sc = device_get_softc(dev);
+	int i;
+
+	/* Reset RMII/RGMII wrapper. */
+	cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
+	while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
+		;
+
+	/* Disable TX and RX interrupts for all cores. */
+	for (i = 0; i < 3; ++i) {
+		cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00);
+		cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00);
+		cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00);
+		cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00);
+	}
+
+	/* Reset CPSW subsystem. */
+	cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
+	while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
+		;
+
+	/* Reset Sliver port 1 and 2 */
+	for (i = 0; i < 2; i++) {
+		/* Reset */
+		cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
+		while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
+			;
+	}
+
+	/* Reset DMA controller. */
+	cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
+	while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
+		;
+
+	/* Disable TX & RX DMA */
+	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0);
+	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0);
+
+	/* Clear all queues. */
+	for (i = 0; i < 8; i++) {
+		cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
+		cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
+		cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
+		cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
+	}
+
+	/* Clear all interrupt Masks */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
+	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
+}
+
+static void
+cpsw_init(void *arg)
+{
+	struct cpsw_softc *sc = arg;
 
 	CPSW_DEBUGF((""));
 	CPSW_GLOBAL_LOCK(sc);
-	cpsw_stop_locked(sc);
+	cpsw_init_locked(arg);
 	CPSW_GLOBAL_UNLOCK(sc);
-	return (0);
 }
 
-static int
-cpsw_resume(device_t dev)
+static void
+cpsw_init_locked(void *arg)
 {
-	/* XXX TODO XXX */
-	device_printf(dev, "%s\n", __FUNCTION__);
-	return (0);
+	struct ifnet *ifp;
+	struct cpsw_softc *sc = arg;
+	struct cpsw_slot *slot;
+	uint32_t i;
+
+	CPSW_DEBUGF((""));
+	ifp = sc->ifp;
+	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+		return;
+
+	getbinuptime(&sc->init_uptime);
+
+	/* Reset the controller. */
+	cpsw_reset(sc);
+
+	/* Enable ALE */
+	cpsw_write_4(sc, CPSW_ALE_CONTROL, 1 << 31 | 1 << 4);
+
+	/* Init Sliver port 1 and 2 */
+	for (i = 0; i < 2; i++) {
+		/* Set Slave Mapping */
+		cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
+		cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i + 1), 0x33221100);
+		cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2);
+		/* Set MACCONTROL for ports 0,1: IFCTL_B(16), IFCTL_A(15),
+		   GMII_EN(5), FULLDUPLEX(1) */
+		/* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */
+		/* Huh?  Docs call bit 0 "Loopback" some places, "FullDuplex" others. */
+		cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), 1 << 15 | 1 << 5 | 1);
+	}
+
+	/* Set Host Port Mapping */
+	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
+	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
+
+	/* Initialize ALE: all ports set to forwarding(3), initialize addrs */
+	for (i = 0; i < 3; i++)
+		cpsw_write_4(sc, CPSW_ALE_PORTCTL(i), 3);
+	cpsw_ale_update_addresses(sc, 1);
+
+	cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
+
+	/* Enable statistics for ports 0, 1 and 2 */
+	cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
+
+	/* Experiment:  Turn off flow control */
+	/* This seems to fix the watchdog resets that have plagued
+	   earlier versions of this driver; I'm not yet sure if there
+	   are negative effects yet. */
+	cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
+
+	/* Make IP hdr aligned with 4 */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2);
+
+	/* Initialize RX Buffer Descriptors */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
+
+	/* Enable TX & RX DMA */
+	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
+	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
+
+	/* Enable Interrupts for core 0 */
+	cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF);
+	cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF);
+	cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x3F);
+
+	/* Enable host Error Interrupt */
+	cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3);
+
+	/* Enable interrupts for RX Channel 0 */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1);
+
+	/* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
+	/* TODO Calculate MDCLK=CLK/(CLKDIV+1) */
+	cpsw_write_4(sc, MDIOCONTROL, 1 << 30 | 1 << 18 | 0xFF);
+
+	/* Select MII in GMII_SEL, Internal Delay mode */
+	//ti_scm_reg_write_4(0x650, 0);
+
+	/* Initialize active queues. */
+	slot = STAILQ_FIRST(&sc->tx.active);
+	if (slot != NULL)
+		cpsw_write_hdp_slot(sc, &sc->tx, slot);
+	slot = STAILQ_FIRST(&sc->rx.active);
+	if (slot != NULL)
+		cpsw_write_hdp_slot(sc, &sc->rx, slot);
+	cpsw_rx_enqueue(sc);
+
+	/* Activate network interface */
+	sc->rx.running = 1;
+	sc->tx.running = 1;
+	sc->watchdog.timer = 0;
+	callout_reset(&sc->watchdog.callout, hz, cpsw_tick, sc);
+	sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
+	sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
 }
 
 static int
@@ -457,376 +938,139 @@ cpsw_shutdown(device_t dev)
 
 	CPSW_DEBUGF((""));
 	CPSW_GLOBAL_LOCK(sc);
-	cpsw_stop_locked(sc);
+	cpsw_shutdown_locked(sc);
 	CPSW_GLOBAL_UNLOCK(sc);
 	return (0);
 }
 
-static int
-cpsw_miibus_ready(struct cpsw_softc *sc)
+static void
+cpsw_rx_teardown_locked(struct cpsw_softc *sc)
 {
-	uint32_t r, retries = CPSW_MIIBUS_RETRIES;
-
-	while (--retries) {
-		r = cpsw_read_4(MDIOUSERACCESS0);
-		if ((r & 1 << 31) == 0)
-			return 1;
-		DELAY(CPSW_MIIBUS_DELAY);
-	}
-	return 0;
-}
+	struct mbuf *received, *next;
+	int i = 0;
 
-static int
-cpsw_miibus_readreg(device_t dev, int phy, int reg)
-{
-	struct cpsw_softc *sc = device_get_softc(dev);
-	uint32_t cmd, r;
-
-	if (!cpsw_miibus_ready(sc)) {
-		device_printf(dev, "MDIO not ready to read\n");
-		return 0;
-	}
-
-	/* Set GO, reg, phy */
-	cmd = 1 << 31 | (reg & 0x1F) << 21 | (phy & 0x1F) << 16;
-	cpsw_write_4(MDIOUSERACCESS0, cmd);
-
-	if (!cpsw_miibus_ready(sc)) {
-		device_printf(dev, "MDIO timed out during read\n");
-		return 0;
-	}
-
-	r = cpsw_read_4(MDIOUSERACCESS0);
-	if((r & 1 << 29) == 0) {
-		device_printf(dev, "Failed to read from PHY.\n");
-		r = 0;
-	}
-	return (r & 0xFFFF);

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***


More information about the svn-src-all mailing list