svn commit: r238973 - head/sys/x86/x86

[Konstantin Belousov]

On Wed, Aug 01, 2012 at 05:26:22PM +0000, Konstantin Belousov wrote:
> Author: kib
> Date: Wed Aug  1 17:26:22 2012
> New Revision: 238973
> URL: http://svn.freebsd.org/changeset/base/238973
> 
> Log:
>   diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c
>   index c253a96..3d8bd30 100644
>   --- a/sys/x86/x86/tsc.c

Oops, I managed to do it: committing with the diff itself as commit log
instead of the log message. Sorry.

It should have been the text

Rdtsc instruction is not synchronized, it seems on some Intel cores it
can bypass even the locked instructions.  As a result, rdtsc executed
on different cores may return unordered TSC values even when the rdtsc
appearance in the instruction sequences is provably ordered.

Similarly to what has been done in r238755 for TSC synchronization
test, add explicit fences right before rdtsc in the timecounters 'get'
functions.  Intel recommends to use LFENCE, while AMD refers to
MFENCE. For VIA follow what Linux does and use LFENCE.  With this
change, I see no reordered reads of TSC on Nehalem.

Change the rmb() to inlined CPUID in the SMP TSC synchronization test.
On i386, locked instruction is used for rmb(), and as noted earlier,
it is not enough. Since i386 machine may not support SSE2, do simplest
possible synchronization with CPUID.

MFC after:	  1 week
Discussed with:	  avg, bde, jkim
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