svn commit: r227850 - head/sys/dev/re

[Pyun YongHyeon]

Author: yongari
Date: Tue Nov 22 23:19:49 2011
New Revision: 227850
URL: http://svn.freebsd.org/changeset/base/227850

Log:
  Writing access to RL_CFG5 register also requires EEPROM write
  access.
  While I'm here, enable WOL through magic packet but disable waking
  up system via unicast, multicast and broadcast frames.  Otherwise,
  multicast or unicast frame(e.g. ICMP echo request) can wake up
  system which is not probably wanted behavior on most environments.
  This was not known as problem because RL_CFG5 register access had
  not effect until this change.
  The capability to wake up system with unicast/multicast frames
  are still set in driver, default off, so users who need that
  feature can still activate it with ifconfig(8).

Modified:
  head/sys/dev/re/if_re.c

Modified: head/sys/dev/re/if_re.c
==============================================================================
--- head/sys/dev/re/if_re.c	Tue Nov 22 21:56:55 2011	(r227849)
+++ head/sys/dev/re/if_re.c	Tue Nov 22 23:19:49 2011	(r227850)
@@ -1590,6 +1590,7 @@ re_attach(device_t dev)
 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &reg) == 0)
 		ifp->if_capabilities |= IFCAP_WOL;
 	ifp->if_capenable = ifp->if_capabilities;
+	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
 	/*
 	 * Don't enable TSO by default.  It is known to generate
 	 * corrupted TCP segments(bad TCP options) under certain
@@ -3622,12 +3623,9 @@ re_setwol(struct rl_softc *sc)
 		v |= RL_CFG3_WOL_MAGIC;
 	CSR_WRITE_1(sc, RL_CFG3, v);
 
-	/* Config register write done. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
-
 	v = CSR_READ_1(sc, RL_CFG5);
-	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
-	v &= ~RL_CFG5_WOL_LANWAKE;
+	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
+	    RL_CFG5_WOL_LANWAKE);
 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
 		v |= RL_CFG5_WOL_UCAST;
 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
@@ -3636,6 +3634,9 @@ re_setwol(struct rl_softc *sc)
 		v |= RL_CFG5_WOL_LANWAKE;
 	CSR_WRITE_1(sc, RL_CFG5, v);
 
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
 	if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
 	    (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);