svn commit: r208111 - head/sys/i386/i386

[Poul-Henning Kamp]

Author: phk
Date: Sat May 15 10:31:11 2010
New Revision: 208111
URL: http://svn.freebsd.org/changeset/base/208111

Log:
  Apply a patch that has been lingering in my inbox for far too long:
  
  On a soekris Net5501, if you do a watchdog -t 16, followed by a watchdog
  -t 0 to disable the watchdog, and then after some time (16s) re-enable
  the watchdog the box reboots immediatly. This prevents also to stop and
  restart watchdogd(8).
  
  This is because when you stop the watchdog, the timer is not stoped,
  only the hard reset is disabled. So when the timer has elapsed, the C2
  event of the timer is set.
  
  But when the hard reset is re-enabled, the event is not cleared and the
  box reboots.
  
  The attached patch stops and resets the counter when the watchdog is
  disabled and do not disable the hard reset of the timer (if the timer
  has elapsed it's too late).
  
  Submitted by:	 Patrick Lamaizière

Modified:
  head/sys/i386/i386/geode.c

Modified: head/sys/i386/i386/geode.c
==============================================================================
--- head/sys/i386/i386/geode.c	Sat May 15 08:57:16 2010	(r208110)
+++ head/sys/i386/i386/geode.c	Sat May 15 10:31:11 2010	(r208111)
@@ -208,14 +208,11 @@ geode_watchdog(void *foo __unused, u_int
 static void
 cs5536_watchdog(void *foo __unused, u_int cmd, int *error)
 {
-	u_int u, p;
+	u_int u, p, s;
 	uint16_t a;
 	uint32_t m;
 
 	a = rdmsr(0x5140000d);
-	m = rdmsr(0x51400029);
-	m &= ~(1 << 24);
-	wrmsr(0x51400029, m);
 
 	u = cmd & WD_INTERVAL;
 	if (u >= 30 && u <= 44) {
@@ -228,12 +225,24 @@ cs5536_watchdog(void *foo __unused, u_in
 		/* reset counter */
 		outw(a + 4, 0);
 		/* Arm reset mechanism */
+		m = rdmsr(0x51400029);
 		m |= (1 << 24);
 		wrmsr(0x51400029, m);
 		/* Start counter */
 		outw(a + 6, 0x8000);
 
 		*error = 0;
+	} else {
+		/* 
+		 * MFGPT_SETUP is write-once
+		 * Check if the counter has been setup
+		 */
+		s = inw(a + 6);
+		if (s & (1 << 12)) {
+			/* Stop and reset counter */
+			outw(a + 6, 0);
+			outw(a + 4, 0);
+		}
 	}
 }