svn commit: r210833 - head/sys/dev/coretemp

[Xin LI]

Author: delphij
Date: Wed Aug  4 00:25:13 2010
New Revision: 210833
URL: http://svn.freebsd.org/changeset/base/210833

Log:
  Catch known CPUs before using IA32_TEMPERATURE_TARGET.
  This way we would have an opportunity to hide the
  Tj(target) value doesn't seem right stuff if we know
  it's not working there.
  
  Add temperature value for Core2 Duo Extreme Mobile that
  I have access to.

Modified:
  head/sys/dev/coretemp/coretemp.c

Modified: head/sys/dev/coretemp/coretemp.c
==============================================================================
--- head/sys/dev/coretemp/coretemp.c	Tue Aug  3 23:11:23 2010	(r210832)
+++ head/sys/dev/coretemp/coretemp.c	Wed Aug  4 00:25:13 2010	(r210833)
@@ -178,34 +178,6 @@ coretemp_attach(device_t dev)
 	 */
 	sc->sc_tjmax = 100;
 
-	/*
-	 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
-	 *
-	 * This method is described in Intel white paper
-	 * "CPU Monitoring With DTS/PECI". (#322683)
-	 */
-	ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
-	if (ret == 0) {
-		tjtarget = (msr >> 16) & 0xff;
-		/*
-		 * On earlier generation of processors, the value obtained
-		 * from IA32_TEMPERATURE_TARGET register is an offset that
-		 * needs to be summed with a model specific base.  It is
-		 * however not clear what these numbers are, with the
-		 * publicly available documents from Intel.
-		 *
-		 * For now, we consider [70, 100]C range, as described in
-		 * #322683, as "reasonable" and accept these values
-		 * whenever the MSR is available for read, regardless the
-		 * CPU model.
-		 */
-		if (tjtarget >= 70 && tjtarget <= 100)
-			sc->sc_tjmax = tjtarget;
-		else
-			device_printf(dev, "Tj(target) value %d does "
-				    "not seem right.\n", tjtarget);
-	}
-
 	if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
 		/*
 		 * On some Core 2 CPUs, there's an undocumented MSR that
@@ -217,6 +189,46 @@ coretemp_attach(device_t dev)
 		msr = rdmsr(MSR_IA32_EXT_CONFIG);
 		if (msr & (1 << 30))
 			sc->sc_tjmax = 85;
+	} else if (cpu_model == 0x17) {
+		switch (cpu_stepping) {
+		case 0x6:	/* Mobile Core 2 Duo */
+			sc->sc_tjmax = 104;
+			break;
+		default:	/* Unknown stepping */
+			break;
+		}
+	} else {
+		/*
+		 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
+		 *
+		 * This method is described in Intel white paper "CPU
+		 * Monitoring With DTS/PECI". (#322683)
+		 */
+		ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
+		if (ret == 0) {
+			tjtarget = (msr >> 16) & 0xff;
+			
+			/*
+			 * On earlier generation of processors, the value
+			 * obtained from IA32_TEMPERATURE_TARGET register is
+			 * an offset that needs to be summed with a model
+			 * specific base.  It is however not clear what
+			 * these numbers are, with the publicly available
+			 * documents from Intel.
+			 *
+			 * For now, we consider [70, 100]C range, as
+			 * described in #322683, as "reasonable" and accept
+			 * these values whenever the MSR is available for
+			 * read, regardless the CPU model.
+			 */
+			if (tjtarget >= 70 && tjtarget <= 100)
+				sc->sc_tjmax = tjtarget;
+			else
+				device_printf(dev, "Tj(target) value %d "
+				    "does not seem right.\n", tjtarget);
+		} else
+			device_printf(dev, "Can not get Tj(target) "
+			    "from your CPU, using 100C.\n");
 	}
 
 	if (bootverbose)