svn commit: r198341 - in head/sys: amd64/amd64 arm/arm arm/mv i386/i386 i386/xen ia64/ia64 kern mips/mips powerpc/aim powerpc/booke powerpc/include powerpc/powerpc sparc64/sparc64 sun4v/sun4v vm

[Marius Strobl]

On Mon, Oct 26, 2009 at 01:53:47PM -0700, Marcel Moolenaar wrote:
> 
> On Oct 26, 2009, at 1:11 PM, Marius Strobl wrote:
> 
> >The cheetah-class CPUs, i.e. USIII and later, take care of
> >I$ coherency themselves, unlike the spitfire ones (see also
> >cheetah_icache_page_inval() vs. spitfire_icache_page_inval()).
> 
> This explains why I didn't see any I-cache coherency issues :-)
> 
> >I currently can't think of any existing code which would
> >ensure I$ consistency after the writes have been performed,
> >not even as a side-effect. The proper solution probalby is to
> >make pmap_sync_icache() a wrapper around icache_page_inval().
> 
> I concur. Do we have any spitfire-based sparc64 boxes in the
> cluster or do you have one?

We don't have any sparc64 machine in the cluster since panther
died although there we're some nice replacements offered for
donation but unfortunately it seems getting a machine into the
cluster is next to impossible.
Do you want something particularly tested on a spitfire-based
machine?

Marius