svn commit: r196445 - head/lib/libpmc

Joseph Koshy jkoshy at
Sun Aug 23 07:24:39 UTC 2009

Author: jkoshy
Date: Sun Aug 23 07:24:39 2009
New Revision: 196445

  Fix typos.


Modified: head/lib/libpmc/pmc.core2.3
--- head/lib/libpmc/pmc.core2.3	Sun Aug 23 06:53:58 2009	(r196444)
+++ head/lib/libpmc/pmc.core2.3	Sun Aug 23 07:24:39 2009	(r196445)
@@ -42,7 +42,7 @@ family CPUs
 CPUs contain PMCs conforming to version 2 of the
 .Tn Intel
 performance measurement architecture.
-These CPUs may contain upto two classes of PMCs:
+These CPUs may contain up to two classes of PMCs:
 .Bl -tag -width "Li PMC_CLASS_IAP"
 Fixed-function counters that count only one hardware event per counter.
@@ -92,13 +92,13 @@ Configure the PMC to increment only if t
 events measured in a cycle is greater than or equal to
 .Ar value .
 .It Li edge
-Configure the PMC to count the number of deasserted to asserted
+Configure the PMC to count the number of de-asserted to asserted
 transitions of the conditions expressed by the other qualifiers.
 If specified, the counter will increment only once whenever a
 condition becomes true, irrespective of the number of clocks during
 which the condition remains true.
 .It Li inv
-Invert the sense of comparision when the
+Invert the sense of comparison when the
 .Dq Li cmask
 qualifier is present, making the counter increment when the number of
 events per cycle is less than the value specified by the
@@ -169,7 +169,7 @@ The default is
 .Dq Li both .
 Events that require a cache coherence qualifier to be specified use an
-additional qualifer
+additional qualifier
 .Dq Li cachestate= Ns Ar state ,
 where argument
 .Ar state
@@ -361,7 +361,7 @@ signal was asserted on the bus.
 .Pq Event 60H
 The number of pending full cache line read transactions on the bus
-occuring in each cycle.
+occurring in each cycle.
 .Op ,agent= Ns Ar agent
 .Op ,core= Ns Ar core
@@ -421,7 +421,7 @@ The number of burst read transactions.
 .Op ,core= Ns Ar core
 .Pq Event 6CH
-The number of completed I/O bus transaactions due to
+The number of completed I/O bus transactions due to
 .Li IN
 .Li OUT
@@ -437,7 +437,7 @@ The number of Read For Ownership bus tra
 .Op ,core= Ns Ar core
 .Pq Event 67H
-The number explicit writeback bus transactions due to dirty line
+The number explicit write-back bus transactions due to dirty line
 .Op ,core= Ns Ar core
@@ -661,7 +661,7 @@ fetch unit.
 .It Li L2_LD Xo
 .Op ,cachestate= Ns Ar state
 .Op ,core= Ns Ar core
-.Op ,prefech= Ns Ar prefetch
+.Op ,prefetch= Ns Ar prefetch
 .Pq Event 29H
 The number of L2 cache read requests from L1 cache and L2
@@ -747,7 +747,7 @@ The number of loads blocked by preceding
 whose data value is not known.
 .Pq Event 03H , Umask 10H
-The numer of load operations that were blocked until retirement.
+The number of load operations that were blocked until retirement.
 .Pq Event 4CH , Umask 00H
 The number of load operations that conflicted with an prefetch to the

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