svn commit: r186009 - in head/sys: amd64/amd64 amd64/include
i386/i386 i386/include
Jung-uk Kim
jkim at FreeBSD.org
Fri Dec 12 23:17:00 UTC 2008
Author: jkim
Date: Fri Dec 12 23:17:00 2008
New Revision: 186009
URL: http://svn.freebsd.org/changeset/base/186009
Log:
Add more CPUID bits from AMD CPUID Specification Rev. 2.28.
Modified:
head/sys/amd64/amd64/identcpu.c
head/sys/amd64/include/specialreg.h
head/sys/i386/i386/identcpu.c
head/sys/i386/include/specialreg.h
Modified: head/sys/amd64/amd64/identcpu.c
==============================================================================
--- head/sys/amd64/amd64/identcpu.c Fri Dec 12 23:13:40 2008 (r186008)
+++ head/sys/amd64/amd64/identcpu.c Fri Dec 12 23:17:00 2008 (r186009)
@@ -322,15 +322,15 @@ printcpuinfo(void)
"\003SVM" /* Secure Virtual Mode */
"\004ExtAPIC" /* Extended APIC register */
"\005CR8" /* CR8 in legacy mode */
- "\006<b5>"
- "\007<b6>"
- "\010<b7>"
+ "\006ABM" /* LZCNT instruction */
+ "\007SSE4A" /* SSE4A */
+ "\010MAS" /* Misaligned SSE mode */
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
- "\012<b9>"
- "\013<b10>"
- "\014<b11>"
- "\015<b12>"
- "\016<b13>"
+ "\012OSVW" /* OS visible workaround */
+ "\013IBS" /* Instruction based sampling */
+ "\014SSE5" /* SSE5 */
+ "\015SKINIT" /* SKINIT/STGI */
+ "\016WDT" /* Watchdog timer */
"\017<b14>"
"\020<b15>"
"\021<b16>"
Modified: head/sys/amd64/include/specialreg.h
==============================================================================
--- head/sys/amd64/include/specialreg.h Fri Dec 12 23:13:40 2008 (r186008)
+++ head/sys/amd64/include/specialreg.h Fri Dec 12 23:17:00 2008 (r186009)
@@ -150,7 +150,15 @@
#define AMDID2_SVM 0x00000004
#define AMDID2_EXT_APIC 0x00000008
#define AMDID2_CR8 0x00000010
+#define AMDID2_ABM 0x00000020
+#define AMDID2_SSE4A 0x00000040
+#define AMDID2_MAS 0x00000080
#define AMDID2_PREFETCH 0x00000100
+#define AMDID2_OSVW 0x00000200
+#define AMDID2_IBS 0x00000400
+#define AMDID2_SSE5 0x00000800
+#define AMDID2_SKINIT 0x00001000
+#define AMDID2_WDT 0x00002000
/*
* CPUID instruction 1 eax info
Modified: head/sys/i386/i386/identcpu.c
==============================================================================
--- head/sys/i386/i386/identcpu.c Fri Dec 12 23:13:40 2008 (r186008)
+++ head/sys/i386/i386/identcpu.c Fri Dec 12 23:17:00 2008 (r186009)
@@ -826,15 +826,15 @@ printcpuinfo(void)
"\003SVM" /* Secure Virtual Mode */
"\004ExtAPIC" /* Extended APIC register */
"\005CR8" /* CR8 in legacy mode */
- "\006<b5>"
- "\007<b6>"
- "\010<b7>"
+ "\006ABM" /* LZCNT instruction */
+ "\007SSE4A" /* SSE4A */
+ "\010MAS" /* Misaligned SSE mode */
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
- "\012<b9>"
- "\013<b10>"
- "\014<b11>"
- "\015<b12>"
- "\016<b13>"
+ "\012OSVW" /* OS visible workaround */
+ "\013IBS" /* Instruction based sampling */
+ "\014SSE5" /* SSE5 */
+ "\015SKINIT" /* SKINIT/STGI */
+ "\016WDT" /* Watchdog timer */
"\017<b14>"
"\020<b15>"
"\021<b16>"
Modified: head/sys/i386/include/specialreg.h
==============================================================================
--- head/sys/i386/include/specialreg.h Fri Dec 12 23:13:40 2008 (r186008)
+++ head/sys/i386/include/specialreg.h Fri Dec 12 23:17:00 2008 (r186009)
@@ -147,7 +147,15 @@
#define AMDID2_SVM 0x00000004
#define AMDID2_EXT_APIC 0x00000008
#define AMDID2_CR8 0x00000010
+#define AMDID2_ABM 0x00000020
+#define AMDID2_SSE4A 0x00000040
+#define AMDID2_MAS 0x00000080
#define AMDID2_PREFETCH 0x00000100
+#define AMDID2_OSVW 0x00000200
+#define AMDID2_IBS 0x00000400
+#define AMDID2_SSE5 0x00000800
+#define AMDID2_SKINIT 0x00001000
+#define AMDID2_WDT 0x00002000
/*
* CPUID instruction 1 eax info
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