socsvn commit: r303014 - soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve

iateaca at FreeBSD.org iateaca at FreeBSD.org
Sun May 15 13:24:02 UTC 2016


Author: iateaca
Date: Sun May 15 13:24:01 2016
New Revision: 303014
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=303014

Log:
  remove the HDAC register defines and use the ones from the hdac_reg.h instead

Modified:
  soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c

Modified: soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c
==============================================================================
--- soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c	Sun May 15 13:17:57 2016	(r303013)
+++ soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c	Sun May 15 13:24:01 2016	(r303014)
@@ -3,6 +3,7 @@
 #include <stdlib.h>
 #include <string.h>
 
+#include "hdac_reg.h"
 #include "pci_emul.h"
 
 /*
@@ -29,77 +30,6 @@
 #define HDA_LAST_OFFSET		(0x80 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
 
 /*
- * HDA Controller Register Offsets
- */
-#define HDAC_GCAP       0x00    /* 2 - Global Capabilities*/
-#define HDAC_VMIN       0x02    /* 1 - Minor Version */
-#define HDAC_VMAJ       0x03    /* 1 - Major Version */
-#define HDAC_OUTPAY     0x04    /* 2 - Output Payload Capability */
-#define HDAC_INPAY      0x06    /* 2 - Input Payload Capability */
-#define HDAC_GCTL       0x08    /* 4 - Global Control */
-#define HDAC_WAKEEN     0x0c    /* 2 - Wake Enable */
-#define HDAC_STATESTS   0x0e    /* 2 - State Change Status */
-#define HDAC_GSTS       0x10    /* 2 - Global Status */
-#define HDAC_OUTSTRMPAY 0x18    /* 2 - Output Stream Payload Capability */
-#define HDAC_INSTRMPAY  0x1a    /* 2 - Input Stream Payload Capability */
-#define HDAC_INTCTL     0x20    /* 4 - Interrupt Control */
-#define HDAC_INTSTS     0x24    /* 4 - Interrupt Status */
-#define HDAC_WALCLK     0x30    /* 4 - Wall Clock Counter */
-#define HDAC_SSYNC      0x38    /* 4 - Stream Synchronization */
-#define HDAC_CORBLBASE  0x40    /* 4 - CORB Lower Base Address */
-#define HDAC_CORBUBASE  0x44    /* 4 - CORB Upper Base Address */
-#define HDAC_CORBWP     0x48    /* 2 - CORB Write Pointer */
-#define HDAC_CORBRP     0x4a    /* 2 - CORB Read Pointer */
-#define HDAC_CORBCTL    0x4c    /* 1 - CORB Control */
-#define HDAC_CORBSTS    0x4d    /* 1 - CORB Status */
-#define HDAC_CORBSIZE   0x4e    /* 1 - CORB Size */
-#define HDAC_RIRBLBASE  0x50    /* 4 - RIRB Lower Base Address */
-#define HDAC_RIRBUBASE  0x54    /* 4 - RIRB Upper Base Address */
-#define HDAC_RIRBWP     0x58    /* 2 - RIRB Write Pointer */
-#define HDAC_RINTCNT    0x5a    /* 2 - Response Interrupt Count */
-#define HDAC_RIRBCTL    0x5c    /* 1 - RIRB Control */
-#define HDAC_RIRBSTS    0x5d    /* 1 - RIRB Status */
-#define HDAC_RIRBSIZE   0x5e    /* 1 - RIRB Size */
-#define HDAC_ICOI       0x60    /* 4 - Immediate Command Output Interface */
-#define HDAC_ICII       0x64    /* 4 - Immediate Command Input Interface */
-#define HDAC_ICIS       0x68    /* 2 - Immediate Command Status */
-#define HDAC_DPIBLBASE  0x70    /* 4 - DMA Position Buffer Lower Base */
-#define HDAC_DPIBUBASE  0x74    /* 4 - DMA Position Buffer Upper Base */
-#define HDAC_SDCTL0     0x80    /* 3 - Stream Descriptor Control */
-#define HDAC_SDCTL1     0x81    /* 3 - Stream Descriptor Control */
-#define HDAC_SDCTL2     0x82    /* 3 - Stream Descriptor Control */
-#define HDAC_SDSTS      0x83    /* 1 - Stream Descriptor Status */
-#define HDAC_SDLPIB     0x84    /* 4 - Link Position in Buffer */
-#define HDAC_SDCBL      0x88    /* 4 - Cyclic Buffer Length */
-#define HDAC_SDLVI      0x8C    /* 2 - Last Valid Index */
-#define HDAC_SDFIFOS    0x90    /* 2 - FIFOS */
-#define HDAC_SDFMT      0x92    /* 2 - fmt */
-#define HDAC_SDBDPL     0x98    /* 4 - Buffer Descriptor Pointer Lower Base */
-#define HDAC_SDBDPU     0x9C    /* 4 - Buffer Descriptor Pointer Upper Base */
-
-#define _HDAC_ISDOFFSET(n, iss, oss)    (0x80 + ((n) * 0x20))
-#define _HDAC_ISDCTL(n, iss, oss)       (0x00 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDSTS(n, iss, oss)       (0x03 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDPICB(n, iss, oss)      (0x04 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDCBL(n, iss, oss)       (0x08 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDLVI(n, iss, oss)       (0x0c + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDFIFOD(n, iss, oss)     (0x10 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDFMT(n, iss, oss)       (0x12 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDBDPL(n, iss, oss)      (0x18 + _HDAC_ISDOFFSET(n, iss, oss))
-#define _HDAC_ISDBDPU(n, iss, oss)      (0x1c + _HDAC_ISDOFFSET(n, iss, oss))
-
-#define _HDAC_OSDOFFSET(n, iss, oss)    (0x80 + ((iss) * 0x20) + ((n) * 0x20))
-#define _HDAC_OSDCTL(n, iss, oss)       (0x00 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDSTS(n, iss, oss)       (0x03 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDPICB(n, iss, oss)      (0x04 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDCBL(n, iss, oss)       (0x08 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDLVI(n, iss, oss)       (0x0c + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDFIFOD(n, iss, oss)     (0x10 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDFMT(n, iss, oss)       (0x12 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDBDPL(n, iss, oss)      (0x18 + _HDAC_OSDOFFSET(n, iss, oss))
-#define _HDAC_OSDBDPU(n, iss, oss)      (0x1c + _HDAC_OSDOFFSET(n, iss, oss))
-
-/*
  * HDA data structures
  */
 


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