socsvn commit: r302382 - soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve

[iateaca at FreeBSD.org]

Author: iateaca
Date: Sun May  8 14:36:45 2016
New Revision: 302382
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=302382

Log:
  add HDA Controller Register Set offsets

Modified:
  soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c

Modified: soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c
==============================================================================
--- soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c	Sun May  8 09:30:36 2016	(r302381)
+++ soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c	Sun May  8 14:36:45 2016	(r302382)
@@ -24,6 +24,56 @@
 #define HDA_INTEL_82801G	0x27d8
 
 /*
+ * HDA Controller Register Offsets
+ */
+#define HDAC_GCAP       0x00    /* 2 - Global Capabilities*/
+#define HDAC_VMIN       0x02    /* 1 - Minor Version */
+#define HDAC_VMAJ       0x03    /* 1 - Major Version */
+#define HDAC_OUTPAY     0x04    /* 2 - Output Payload Capability */
+#define HDAC_INPAY      0x06    /* 2 - Input Payload Capability */
+#define HDAC_GCTL       0x08    /* 4 - Global Control */
+#define HDAC_WAKEEN     0x0c    /* 2 - Wake Enable */
+#define HDAC_STATESTS   0x0e    /* 2 - State Change Status */
+#define HDAC_GSTS       0x10    /* 2 - Global Status */
+#define HDAC_OUTSTRMPAY 0x18    /* 2 - Output Stream Payload Capability */
+#define HDAC_INSTRMPAY  0x1a    /* 2 - Input Stream Payload Capability */
+#define HDAC_INTCTL     0x20    /* 4 - Interrupt Control */
+#define HDAC_INTSTS     0x24    /* 4 - Interrupt Status */
+#define HDAC_WALCLK     0x30    /* 4 - Wall Clock Counter */
+#define HDAC_SSYNC      0x38    /* 4 - Stream Synchronization */
+#define HDAC_CORBLBASE  0x40    /* 4 - CORB Lower Base Address */
+#define HDAC_CORBUBASE  0x44    /* 4 - CORB Upper Base Address */
+#define HDAC_CORBWP     0x48    /* 2 - CORB Write Pointer */
+#define HDAC_CORBRP     0x4a    /* 2 - CORB Read Pointer */
+#define HDAC_CORBCTL    0x4c    /* 1 - CORB Control */
+#define HDAC_CORBSTS    0x4d    /* 1 - CORB Status */
+#define HDAC_CORBSIZE   0x4e    /* 1 - CORB Size */
+#define HDAC_RIRBLBASE  0x50    /* 4 - RIRB Lower Base Address */
+#define HDAC_RIRBUBASE  0x54    /* 4 - RIRB Upper Base Address */
+#define HDAC_RIRBWP     0x58    /* 2 - RIRB Write Pointer */
+#define HDAC_RINTCNT    0x5a    /* 2 - Response Interrupt Count */
+#define HDAC_RIRBCTL    0x5c    /* 1 - RIRB Control */
+#define HDAC_RIRBSTS    0x5d    /* 1 - RIRB Status */
+#define HDAC_RIRBSIZE   0x5e    /* 1 - RIRB Size */
+#define HDAC_ICOI       0x60    /* 4 - Immediate Command Output Interface */
+#define HDAC_ICII       0x64    /* 4 - Immediate Command Input Interface */
+#define HDAC_ICIS       0x68    /* 2 - Immediate Command Status */
+#define HDAC_DPIBLBASE  0x70    /* 4 - DMA Position Buffer Lower Base */
+#define HDAC_DPIBUBASE  0x74    /* 4 - DMA Position Buffer Upper Base */
+#define HDAC_SDCTL0     0x80    /* 3 - Stream Descriptor Control */
+#define HDAC_SDCTL1     0x81    /* 3 - Stream Descriptor Control */
+#define HDAC_SDCTL2     0x82    /* 3 - Stream Descriptor Control */
+#define HDAC_SDSTS      0x83    /* 1 - Stream Descriptor Status */
+#define HDAC_SDLPIB     0x84    /* 4 - Link Position in Buffer */
+#define HDAC_SDCBL      0x88    /* 4 - Cyclic Buffer Length */
+#define HDAC_SDLVI      0x8C    /* 2 - Last Valid Index */
+#define HDAC_SDFIFOS    0x90    /* 2 - FIFOS */
+#define HDAC_SDFMT      0x92    /* 2 - fmt */
+#define HDAC_SDBDPL     0x98    /* 4 - Buffer Descriptor Pointer Lower Base */
+#define HDAC_SDBDPU     0x9C    /* 4 - Buffer Descriptor Pointer Upper Base */
+
+
+/*
  * HDA data structures
  */