socsvn commit: r302358 - soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve

[iateaca at FreeBSD.org]

Author: iateaca
Date: Sat May  7 19:19:23 2016
New Revision: 302358
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=302358

Log:
  probe the HDA controller - set the PCI configuration space, allocate BAR0 memory addresses and request IRQ

Modified:
  soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c

Modified: soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c
==============================================================================
--- soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c	Sat May  7 18:58:07 2016	(r302357)
+++ soc2015/iateaca/bhyve-ne2000-head/usr.sbin/bhyve/pci_hda.c	Sat May  7 19:19:23 2016	(r302358)
@@ -7,7 +7,7 @@
 /*
  * HDA Debug Log
  */
-#define DEBUG_HDA			0
+#define DEBUG_HDA			1
 #if DEBUG_HDA == 1
 static FILE *dbg;
 #define DPRINTF(fmt, arg...)						\
@@ -20,6 +20,8 @@
 /*
  * HDA defines
  */
+#define INTEL_VENDORID		0x8086
+#define HDA_INTEL_82801G	0x27d8
 
 /*
  * HDA data structures
@@ -63,6 +65,28 @@
 static int
 pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
 {
+	assert(ctx != NULL);
+	assert(pi != NULL);
+
+#if DEBUG_HDA == 1
+	dbg = fopen("/tmp/bhyve_hda.log", "w+");
+#endif
+
+	DPRINTF("PCI HDA\n");
+
+	pci_set_cfgdata16(pi, PCIR_VENDOR, INTEL_VENDORID);
+	pci_set_cfgdata16(pi, PCIR_DEVICE, HDA_INTEL_82801G);
+
+	pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_MULTIMEDIA_HDA);
+	pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_MULTIMEDIA);
+
+	/* TODO check the right size */
+	/* allocate one BAR register for the Memory address offsets */
+	pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, 0x0fff);
+
+	/* allocate an IRQ pin for our slot */
+	pci_lintr_request(pi);
+
 	return 0;
 }
 
@@ -70,6 +94,10 @@
 pci_hda_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
 		int baridx, uint64_t offset, int size, uint64_t value)
 {
+	assert(baridx == 0);
+
+	DPRINTF("offset: 0x%lx size: %d\n", offset, size);
+
 	return;
 }
 
@@ -77,6 +105,10 @@
 pci_hda_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
 		int baridx, uint64_t offset, int size)
 {
+	assert(baridx == 0);
+
+	DPRINTF("offset: 0x%lx size: %d\n", offset, size);
+
 	return 0;
 }