socsvn commit: r299444 - soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm

[mihai at FreeBSD.org]

Author: mihai
Date: Wed Mar  2 17:02:42 2016
New Revision: 299444
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=299444

Log:
  sys: arm: vmm: vgic.h: add vars to save the state of the distributor

Modified:
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/vgic.h

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/vgic.h
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/vgic.h	Wed Mar  2 16:36:24 2016	(r299443)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/vgic.h	Wed Mar  2 17:02:42 2016	(r299444)
@@ -1,18 +1,48 @@
 #ifndef _VMM_VGIC_H_
 #define	_VMM_VGIC_H_
 
+
+#define VGIC_NR_IRQ		128
+#define VGIC_NR_SGI		16
+#define VGIC_NR_PPI		16
+#define VGIC_NR_PRV_IRQ	(VGIC_NR_SGI + VGIC_NR_PPI)
+#define VGIC_NR_SHR_IRQ	(VGIC_NR_IRQ - VGIC_NR_PRV_IRQ)
+#define VGIC_MAXCPU		VM_MAXCPU
 #define VGIC_LR_NUM	64
+
+
 struct vm;
 struct vm_exit;
 
 struct vgic_distributor {
-	uint64_t	distributor_base;
-	uint64_t	cpu_int_base;
+	uint64_t distributor_base;
+	uint64_t cpu_int_base;
+
+	/* Bitmaps for IRQ state in the distributor*/
+
+	/* Interrupt enabled */
+	uint32_t irq_enabled_prv[VGIC_MAXCPU][VGIC_NR_PRV_IRQ / sizeof(uint32_t)];
+	uint32_t irq_enabled_shr[VGIC_NR_SHR_IRQ / sizeof(uint32_t)];
+	
+	/* Interrupt level */
+	uint32_t irq_state_prv[VGIC_MAXCPU][VGIC_NR_PRV_IRQ / sizeof(uint32_t)];
+	uint32_t irq_state_shr[VGIC_NR_SHR_IRQ / sizeof(uint32_t)];
+
+	/* Level interrupts in progress */
+	uint32_t irq_active_prv[VGIC_MAXCPU][VGIC_NR_PRV_IRQ / sizeof(uint32_t)];
+	uint32_t irq_active_shr[VGIC_NR_SHR_IRQ / sizeof(uint32_t)];
+
+	/* Configure type of IRQ: level or edge triggered */
+	uint32_t irq_conf_prv[VGIC_MAXCPU][VGIC_NR_PRV_IRQ / sizeof(uint32_t)];
+	uint32_t irq_conf_shr[VGIC_NR_SHR_IRQ / sizeof(uint32_t)];
 
-	int		nr_irqs;
 };
 
 struct vgic_cpu_int {
+	/* Bitmaps for pending IRQs */
+	uint32_t	pending_prv[VGIC_NR_PRV_IRQ / sizeof(uint32_t)];
+	uint32_t	pending_shr[VGIC_NR_SHR_IRQ / sizeof(uint32_t)];
+	
 	uint64_t	virtual_int_ctrl;
 	uint32_t	lr_num;
 	uint32_t	hcr;
@@ -22,6 +52,8 @@
 	uint64_t	elsr;
 	uint32_t	apr;
 	uint32_t	lr[VGIC_LR_NUM];
+	uint8_t		lr_used[VGIC_LR_NUM];
+	uint8_t		irq_to_lr[VGIC_NR_IRQ];
 };
 
 int vgic_hyp_init(void);