socsvn commit: r306349 - soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve
iateaca at FreeBSD.org
iateaca at FreeBSD.org
Sat Jul 16 17:40:43 UTC 2016
Author: iateaca
Date: Sat Jul 16 17:40:41 2016
New Revision: 306349
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=306349
Log:
increase the size of the register space at 0x2084 + IOSS_NO necessary for the LPIB Aliases
set reset values for the VMAJ, OUTPAY, INPAY and SDFIFOS registers
implement the hda_set_pib funtion in order to set the PIB value in LPIB, LPIB Alias and dma_pib_vaddr memroy region
select the Intel HDA mode in the PCI Conf space
M bhyve/hda_codec.c
M bhyve/pci_hda.c
M bhyve/pci_hda.h
Modified:
soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/hda_codec.c
soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c
soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.h
Modified: soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/hda_codec.c
==============================================================================
--- soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/hda_codec.c Sat Jul 16 15:52:14 2016 (r306348)
+++ soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/hda_codec.c Sat Jul 16 17:40:41 2016 (r306349)
@@ -69,7 +69,7 @@
#define HDA_CONFIG_DEFAULTCONF_COLOR_BLACK (0x01 << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT)
-#define HDA_CODEC_BUF_SIZE 0x100
+#define HDA_CODEC_BUF_SIZE HDA_FIFO_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
Modified: soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c
==============================================================================
--- soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c Sat Jul 16 15:52:14 2016 (r306348)
+++ soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.c Sat Jul 16 17:40:41 2016 (r306349)
@@ -9,6 +9,7 @@
/*
* HDA defines
*/
+#define PCIR_HDCTL 0x40
#define INTEL_VENDORID 0x8086
#define HDA_INTEL_82801G 0x27d8
@@ -16,7 +17,8 @@
#define HDA_OSS_NO 0x04
#define HDA_ISS_NO 0x04
#define HDA_CODEC_MAX 0x0f
-#define HDA_LAST_OFFSET (0x80 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
+#define HDA_LAST_OFFSET (0x2084 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
+#define HDA_SET_REG_TABLE_SZ (0x80 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
#define HDA_CORB_ENTRY_LEN 0x04
#define HDA_RIRB_ENTRY_LEN 0x08
#define HDA_BDL_ENTRY_LEN 0x10
@@ -187,6 +189,8 @@
static int
hda_transfer(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir, void *buf, size_t count);
+static void
+hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib);
static uint64_t hda_get_clock_ns(void);
/*
@@ -233,7 +237,7 @@
HDAC_OSTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
HDAC_OSTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
- [HDA_LAST_OFFSET] = NULL,
+ [HDA_SET_REG_TABLE_SZ] = NULL,
};
static const uint16_t hda_corb_sizes[] = {
@@ -524,6 +528,9 @@
static void
hda_reset_regs(struct hda_softc *sc)
{
+ uint32_t off = 0;
+ uint8_t i;
+
DPRINTF("Reset the HDA controller registers ...\n");
memset(sc->regs, 0, sizeof(sc->regs));
@@ -532,10 +539,17 @@
HDAC_GCAP_64OK |
(HDA_ISS_NO << HDAC_GCAP_ISS_SHIFT) |
(HDA_OSS_NO << HDAC_GCAP_OSS_SHIFT));
-
+ hda_set_reg_by_offset(sc, HDAC_VMAJ, 0x01);
+ hda_set_reg_by_offset(sc, HDAC_OUTPAY, 0x3c);
+ hda_set_reg_by_offset(sc, HDAC_INPAY, 0x1d);
hda_set_reg_by_offset(sc, HDAC_CORBSIZE, HDAC_CORBSIZE_CORBSZCAP_256 | HDAC_CORBSIZE_CORBSIZE_256);
hda_set_reg_by_offset(sc, HDAC_RIRBSIZE, HDAC_RIRBSIZE_RIRBSZCAP_256 | HDAC_RIRBSIZE_RIRBSIZE_256);
+ for (i = 0; i < HDA_IOSS_NO; i++) {
+ off = hda_get_offset_stream(i);
+ hda_set_reg_by_offset(sc, off + HDAC_SDFIFOS, HDA_FIFO_SIZE);
+ }
+
return;
}
@@ -637,9 +651,8 @@
st->dir = dir;
st->bp = 0;
st->be = 0;
- hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, 0);
- if (sc->dma_pib_vaddr)
- *(uint32_t *)(sc->dma_pib_vaddr + stream_ind * HDA_DMA_PIB_ENTRY_LEN) = 0;
+
+ hda_set_pib(sc, stream_ind, 0);
st->run = 1;
@@ -896,13 +909,17 @@
struct hda_codec_cmd_ctl *corb = NULL;
if (value & HDAC_CORBCTL_CORBRUN) {
- err = hda_corb_start(sc);
- assert(!err);
+ if (!(old & HDAC_CORBCTL_CORBRUN)) {
+ err = hda_corb_start(sc);
+ assert(!err);
+ }
} else {
corb = &sc->corb;
memset(corb, 0, sizeof(*corb));
}
+ hda_corb_run(sc);
+
return;
}
@@ -1149,9 +1166,7 @@
}
}
- hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, lpib);
- if (sc->dma_pib_vaddr)
- *(uint32_t *)(sc->dma_pib_vaddr + stream_ind * HDA_DMA_PIB_ENTRY_LEN) = lpib;
+ hda_set_pib(sc, stream_ind, lpib);
if (irq) {
hda_set_field_by_offset(sc, off + HDAC_SDSTS, HDAC_SDSTS_BCIS, HDAC_SDSTS_BCIS);
@@ -1161,6 +1176,19 @@
return 0;
}
+static void
+hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib)
+{
+ uint32_t off = hda_get_offset_stream(stream_ind);
+
+ hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, pib);
+ hda_set_reg_by_offset(sc, 0x2000 + off + HDAC_SDLPIB, pib); /* LPIB Alias */
+ if (sc->dma_pib_vaddr)
+ *(uint32_t *)(sc->dma_pib_vaddr + stream_ind * HDA_DMA_PIB_ENTRY_LEN) = pib;
+
+ return;
+}
+
static uint64_t hda_get_clock_ns(void)
{
struct timespec ts;
@@ -1189,9 +1217,11 @@
pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_MULTIMEDIA_HDA);
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_MULTIMEDIA);
- /* TODO check the right size */
+ /* select the Intel HDA mode */
+ pci_set_cfgdata8(pi, PCIR_HDCTL, 0x01);
+
/* allocate one BAR register for the Memory address offsets */
- pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, 0x1000);
+ pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, HDA_LAST_OFFSET);
/* allocate an IRQ pin for our slot */
pci_lintr_request(pi);
Modified: soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.h
==============================================================================
--- soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.h Sat Jul 16 15:52:14 2016 (r306348)
+++ soc2016/iateaca/bhyve-hda-head/usr.sbin/bhyve/pci_hda.h Sat Jul 16 17:40:41 2016 (r306349)
@@ -27,6 +27,8 @@
#define DPRINTF(fmt, arg...)
#endif
+#define HDA_FIFO_SIZE 0x100
+
struct hda_softc;
struct hda_codec_class;
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