socsvn commit: r287374 - in soc2015/mihai/bhyve-on-arm-head/sys: arm/arm arm/conf conf

[mihai at FreeBSD.org]

Author: mihai
Date: Sat Jun 20 11:34:31 2015
New Revision: 287374
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=287374

Log:
  soc2015: mihai: bhyve-on-arm-head: install stub handler for HYP mode in order to bhyve call it later to make the real initialization

Added:
  soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/hypervisor-stub.S
Modified:
  soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/locore-v6.S
  soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1
  soc2015/mihai/bhyve-on-arm-head/sys/conf/files.arm

Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/hypervisor-stub.S
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/hypervisor-stub.S	Sat Jun 20 11:34:31 2015	(r287374)
@@ -0,0 +1,57 @@
+#include "assym.s"
+#include <sys/syscall.h>
+#include <machine/asm.h>
+#include <machine/asmacros.h>
+#include <machine/armreg.h>
+#include <machine/sysreg.h>
+#include <machine/cpuconf.h>
+
+ASENTRY_NP(_hypervisor_stub_vect_install)
+
+	/* If we are not in SVC mode than return */
+	mrs	r0, cpsr
+	and	r0, r0, #(PSR_MODE)
+	cmp	r0, #(PSR_HYP32_MODE)
+	movne	pc, lr
+
+	/* Install hypervisor stub vectors. */
+	ldr	r0, =_hypervisor_stub_vect
+	mcr	p15, 4, r0, c12, c0, 0	@ set HVBAR
+
+	/* Disable all the traps in the hypervisor. */
+	mov	r0, #0
+	mcr	p15, 4, r0, c1, c1, 0	@ HCR
+	mcr	p15, 4, r0, c1, c1, 2	@ HCPTR
+	mcr	p15, 4, r0, c1, c1, 3	@ HSTR
+	mcr	p15, 4, r0, c1, c0, 0	@ HSCTLR
+
+	/* Don't disable access to perf-mon from PL0,1 */ 
+	mrc	p15, 4, r0, c1, c1, 1	@ HDCR
+	and	r0, #0x1f		@ Preserve HPMN
+	mcr	p15, 4, r0, c1, c1, 1	@ HDCR
+
+	mov	pc, lr
+END(_hypervisor_stub_vect_install)
+
+ASENTRY_NP(_hypervisor_stub_trap)
+	/*
+	 * If the first parameter is -1 than return the
+	 * exception vector (HVBAR), otherwise set it to
+	 * the value of it.
+	 */
+	cmp	r0, #-1
+	mrceq	p15, 4, r0, c12, c0, 0	@ get HVBAR
+	mcrne	p15, 4, r0, c12, c0, 0	@ set HVBAR
+	eret
+END(_hypervisor_stub_trap)
+
+
+_C_LABEL(_hypervisor_stub_vect):
+	.word 0 /* Reset */
+	.word 0 /* undev */
+	.word 0 /* SMC */
+	.word 0 /* PABT */
+	.word 0 /* DABT */
+	b	_hypervisor_stub_trap /* HYP-Mode */
+	.word 0 /* FIQ */
+	.word 0 /* IRQ */

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/locore-v6.S
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/locore-v6.S	Sat Jun 20 09:06:48 2015	(r287373)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/locore-v6.S	Sat Jun 20 11:34:31 2015	(r287374)
@@ -67,9 +67,30 @@
 btext:
 ASENTRY_NP(_start)
 	STOP_UNWINDING		/* Can't unwind into the bootloader! */
-
-	/* Setup status register for supervisor mode, interrupts disabled */
-	msr     cpsr_fc, #0xd3
+	
+	# If HYP-MODE is active, install an exception vector stub
+	bl _hypervisor_stub_vect_install
+
+	# Return to SVC
+	mrs	r0, cpsr
+	eor	r0, r0, #(PSR_HYP32_MODE)
+	tst	r0, #(PSR_MODE)
+	bic	r0, r0, #(PSR_MODE)
+	orr	r0, r0, #(PSR_F | PSR_I | PSR_SVC32_MODE)
+	/* If we are not in HYP, we disable all interrupts and set SCVN mode */
+	bne	1f
+	/*
+	 * If we are in HYP mode set the LR from HYP-Mode to the
+	 * address of label 2: and the SPSR to the value of CPSR
+	 */
+	orr	r0, r0, #(PSR_A)
+	adr	lr, 2f
+	msr	ELR_hyp, lr
+	msr	spsr_fsxc, r0
+	eret
+1:
+	msr	cpsr_c, r0
+2:
 
 	mov	r8, r0		/* 0 or boot mode from boot2 */
 	mov	r9, r1		/* Save Machine type */

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1	Sat Jun 20 09:06:48 2015	(r287373)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1	Sat Jun 20 11:34:31 2015	(r287374)
@@ -8,7 +8,7 @@
 
 cpu		CPU_CORTEXA
 machine		arm armv6
-makeoptions	CONF_CFLAGS="-march=armv7a"
+makeoptions	CONF_CFLAGS="-mcpu=cortex-a15"
 
 include 	"std.armv6"
 

Modified: soc2015/mihai/bhyve-on-arm-head/sys/conf/files.arm
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/conf/files.arm	Sat Jun 20 09:06:48 2015	(r287373)
+++ soc2015/mihai/bhyve-on-arm-head/sys/conf/files.arm	Sat Jun 20 11:34:31 2015	(r287374)
@@ -43,6 +43,7 @@
 arm/arm/in_cksum_arm.S		optional	inet | inet6
 arm/arm/intr.c			standard
 arm/arm/locore.S		standard	no-obj
+arm/arm/hypervisor-stub.S	standard
 arm/arm/machdep.c		standard
 arm/arm/mem.c			optional	mem
 arm/arm/minidump_machdep.c	optional	mem