socsvn commit: r288371 - soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm
mihai at FreeBSD.org
mihai at FreeBSD.org
Tue Jul 14 11:47:15 UTC 2015
Author: mihai
Date: Tue Jul 14 11:47:13 2015
New Revision: 288371
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=288371
Log:
soc2015: mihai: bhyve: sys: arm: vmm: hyp_helpers.h: fix dumb comments
Modified:
soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h
Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h Tue Jul 14 10:49:36 2015 (r288370)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h Tue Jul 14 11:47:13 2015 (r288371)
@@ -23,7 +23,7 @@
/* r0 - address of the hypctx */ \
add r2, r0, #HYPCTX_REGS_R(3); \
stm r2, {r3-r12}; \
- pop {r3-r5}; @ Get r0-r2 from the stack \
+ pop {r3-r5}; /* Get r0-r2 from the stack */ \
add r2, r0, #HYPCTX_REGS_R(0); \
stm r2, {r3-r5}; \
\
@@ -131,64 +131,64 @@
msr ELR_hyp, r2
#define load_cp15_regs_batch1 \
- mrc p15, 0, r2, c1, c0, 0; @ SCTLR \
- mrc p15, 0, r3, c1, c0, 2; @ CPACR \
- mrc p15, 0, r4, c2, c0, 2; @ TTBCR \
- mrc p15, 0, r5, c3, c0, 0; @ DACR \
- mrrc p15, 0, r6, r7, c2; @ TTBR 0 \
- mrrc p15, 1, r8, r9, c2; @ TTBR 1 \
- mrc p15, 0, r10, c10, c2, 0; @ PRRR \
- mrc p15, 0, r11, c10, c2, 1; @ NMRR \
- mrc p15, 2, r12, c0, c0, 0 @ CSSELR
+ mrc p15, 0, r2, c1, c0, 0; /* SCTLR */ \
+ mrc p15, 0, r3, c1, c0, 2; /* CPACR */ \
+ mrc p15, 0, r4, c2, c0, 2; /* TTBCR */ \
+ mrc p15, 0, r5, c3, c0, 0; /* DACR */ \
+ mrrc p15, 0, r6, r7, c2; /* TTBR 0 */ \
+ mrrc p15, 1, r8, r9, c2; /* TTBR 1 */ \
+ mrc p15, 0, r10, c10, c2, 0; /* PRRR */ \
+ mrc p15, 0, r11, c10, c2, 1; /* NMRR */ \
+ mrc p15, 2, r12, c0, c0, 0 /* CSSELR */
#define load_cp15_regs_batch2 \
- mrc p15, 0, r2, c13, c0, 1; @ CID \
- mrc p15, 0, r3, c13, c0, 2; @ TID_URW \
- mrc p15, 0, r4, c13, c0, 3; @ TID_URO \
- mrc p15, 0, r5, c13, c0, 4; @ TID_PRIV \
- mrc p15, 0, r6, c5, c0, 0; @ DFSR \
- mrc p15, 0, r7, c5, c0, 1; @ IFSR \
- mrc p15, 0, r8, c5, c1, 0; @ ADFSR \
- mrc p15, 0, r9, c5, c1, 1; @ AIFSR \
- mrc p15, 0, r10, c6, c0, 0; @ DFAR \
- mrc p15, 0, r11, c6, c0, 2; @ IFAR \
- mrc p15, 0, r12, c12, c0, 0 @ VBAR
+ mrc p15, 0, r2, c13, c0, 1; /* CID */ \
+ mrc p15, 0, r3, c13, c0, 2; /* TID_URW */ \
+ mrc p15, 0, r4, c13, c0, 3; /* TID_URO */ \
+ mrc p15, 0, r5, c13, c0, 4; /* TID_PRIV */ \
+ mrc p15, 0, r6, c5, c0, 0; /* DFSR */ \
+ mrc p15, 0, r7, c5, c0, 1; /* IFSR */ \
+ mrc p15, 0, r8, c5, c1, 0; /* ADFSR */ \
+ mrc p15, 0, r9, c5, c1, 1; /* AIFSR */ \
+ mrc p15, 0, r10, c6, c0, 0; /* DFAR */ \
+ mrc p15, 0, r11, c6, c0, 2; /* IFAR */ \
+ mrc p15, 0, r12, c12, c0, 0 /* VBAR */
#define load_cp15_regs_batch3 \
- mrc p15, 0, r2, c14, c1, 0; @ CNTKCTL \
- mrrc p15, 0, r3, r4, c7; @ PAR \
- mrc p15, 0, r5, c10, c3, 0; @ AMAIR0 \
- mrc p15, 0, r6, c10, c3, 1 @ AMAIR1
+ mrc p15, 0, r2, c14, c1, 0; /* CNTKCTL */ \
+ mrrc p15, 0, r3, r4, c7; /* PAR */ \
+ mrc p15, 0, r5, c10, c3, 0; /* AMAIR0 */ \
+ mrc p15, 0, r6, c10, c3, 1 /* AMAIR1 */
#define store_cp15_regs_batch1 \
- mcr p15, 0, r2, c1, c0, 0; @ SCTLR \
- mcr p15, 0, r3, c1, c0, 2; @ CPACR \
- mcr p15, 0, r4, c2, c0, 2; @ TTBCR \
- mcr p15, 0, r5, c3, c0, 0; @ DACR \
- mcrr p15, 0, r6, r7, c2; @ TTBR 0 \
- mcrr p15, 1, r8, r9, c2; @ TTBR 1 \
- mcr p15, 0, r10, c10, c2, 0; @ PRRR \
- mcr p15, 0, r11, c10, c2, 1; @ NMRR \
- mcr p15, 2, r12, c0, c0, 0 @ CSSELR
+ mcr p15, 0, r2, c1, c0, 0; /* SCTLR */ \
+ mcr p15, 0, r3, c1, c0, 2; /* CPACR */ \
+ mcr p15, 0, r4, c2, c0, 2; /* TTBCR */ \
+ mcr p15, 0, r5, c3, c0, 0; /* DACR */ \
+ mcrr p15, 0, r6, r7, c2; /* TTBR 0 */ \
+ mcrr p15, 1, r8, r9, c2; /* TTBR 1 */ \
+ mcr p15, 0, r10, c10, c2, 0; /* PRRR */ \
+ mcr p15, 0, r11, c10, c2, 1; /* NMRR */ \
+ mcr p15, 2, r12, c0, c0, 0 /* CSSELR */
#define store_cp15_regs_batch2 \
- mcr p15, 0, r2, c13, c0, 1; @ CID \
- mcr p15, 0, r3, c13, c0, 2; @ TID_URW \
- mcr p15, 0, r4, c13, c0, 3; @ TID_URO \
- mcr p15, 0, r5, c13, c0, 4; @ TID_PRIV \
- mcr p15, 0, r6, c5, c0, 0; @ DFSR \
- mcr p15, 0, r7, c5, c0, 1; @ IFSR \
- mcr p15, 0, r8, c5, c1, 0; @ ADFSR \
- mcr p15, 0, r9, c5, c1, 1; @ AIFSR \
- mcr p15, 0, r10, c6, c0, 0; @ DFAR \
- mcr p15, 0, r11, c6, c0, 2; @ IFAR \
- mcr p15, 0, r12, c12, c0, 0 @ VBAR
+ mcr p15, 0, r2, c13, c0, 1; /* CID */ \
+ mcr p15, 0, r3, c13, c0, 2; /* TID_URW */ \
+ mcr p15, 0, r4, c13, c0, 3; /* TID_URO */ \
+ mcr p15, 0, r5, c13, c0, 4; /* TID_PRIV */ \
+ mcr p15, 0, r6, c5, c0, 0; /* DFSR */ \
+ mcr p15, 0, r7, c5, c0, 1; /* IFSR */ \
+ mcr p15, 0, r8, c5, c1, 0; /* ADFSR */ \
+ mcr p15, 0, r9, c5, c1, 1; /* AIFSR */ \
+ mcr p15, 0, r10, c6, c0, 0; /* DFAR */ \
+ mcr p15, 0, r11, c6, c0, 2; /* IFAR */ \
+ mcr p15, 0, r12, c12, c0, 0 /* VBAR */
#define store_cp15_regs_batch3 \
- mcr p15, 0, r2, c14, c1, 0; @ CNTKCTL \
- mcrr p15, 0, r3, r4, c7; @ PAR \
- mcr p15, 0, r5, c10, c3, 0; @ AMAIR0 \
- mcr p15, 0, r6, c10, c3, 1 @ AMAIR1
+ mcr p15, 0, r2, c14, c1, 0; /* CNTKCTL */ \
+ mcrr p15, 0, r3, r4, c7; /* PAR */ \
+ mcr p15, 0, r5, c10, c3, 0; /* AMAIR0 */ \
+ mcr p15, 0, r6, c10, c3, 1 /* AMAIR1 */
#define store_guest_cp15_regs_batch1 \
str r2, [r0, #HYPCTX_CP15_SCTLR]; \
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