socsvn commit: r287803 - soc2015/pratiksinghal/cubie-head/sys/arm/allwinner
pratiksinghal at FreeBSD.org
pratiksinghal at FreeBSD.org
Wed Jul 1 09:58:27 UTC 2015
Author: pratiksinghal
Date: Wed Jul 1 09:58:26 2015
New Revision: 287803
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=287803
Log:
1) Added the code for separate DMA module
2) The code committed is yet to be tested on hardware.
Added:
soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c
soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h
Added: soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c Wed Jul 1 09:58:26 2015 (r287803)
@@ -0,0 +1,332 @@
+/*-
+ * Copyright (c) 2015 Pratik Singhal
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+#include <sys/cdefs.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include "a10_dma.h"
+
+enum a10_dma_channel_type {
+ NDMA,
+ DDMA
+} ;
+
+struct a10_dma_channel {
+ enum a10_dma_channel_type ch_type;
+ uint32_t ch_index;
+ void (*ch_a10_dma_intr_handle) (void *);
+ void * ch_a10_dma_intr_args;
+ bus_size_t ch_offset;
+};
+
+struct a10_dma_softc {
+ device_t a10_dma_dev;
+ bus_space_tag_t a10_dma_bst;
+ bus_space_handle_t a10_dma_bsh;
+ struct resource * a10_dma_memory_resource;
+ struct resource * a10_dma_irq_resource;
+ void* a10_dma_intrhand;
+ int a10_dma_mem_rid;
+ int a10_dma_irq_rid;
+ struct mtx a10_dma_mtx;
+ struct a10_dma_channel a10_ndma_channels[NNDMA];
+ struct a10_dma_channel a10_ddma_channels[NDDMA];
+} ;
+
+static struct a10_dma_softc *sc;
+static int a10_dma_probe(device_t);
+static int a10_dma_attach(device_t);
+static int a10_dma_detach(device_t);
+static void a10_dma_intr(void *);
+static struct a10_dma_channel * a10_dma_alloc_channel(uint32_t, void (*) (void *), void *);
+static int a10_dma_start_transfer(struct a10_dma_channel *, bus_addr_t, bus_addr_t, bus_size_t);
+static void a10_dma_free_channel(struct a10_dma_channel *);
+static void a10_dma_set_config(struct a10_dma_channel *, uint32_t);
+static uint32_t a10_dma_get_config(struct a10_dma_channel *);
+static void a10_dma_halt(struct a10_dma_channel *);
+
+#define A10_DMA_LOCK(_sc) mtx_lock(&(_sc)->a10_dma_mtx)
+#define A10_DMA_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_dma_mtx)
+#define A10_DMA_READ_4(_sc, _reg) \
+ bus_space_read_4((_sc)->a10_dma_bst, (_sc)->a10_dma_bsh, _reg)
+#define A10_DMA_WRITE_4(_sc,_reg, _value) \
+ bus_space_write_4((_sc)->a10_dma_bst, (_sc)->a10_dma_bsh, _reg, _value)
+#define A10_DMACH_READ_4(_sc, _reg) \
+ A10_DMA_READ_4(sc, (_reg) + (_sc)->ch_offset)
+#define A10_DMACH_WRITE_4(_sc, _reg, _value) \
+ A10_DMA_WRITE_4(sc, (_reg) + (_sc)->ch_offset, _value)
+
+
+static int
+a10_dma_probe(device_t dev)
+{
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO) ;
+ if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-dma"))
+ return (ENXIO) ;
+ device_set_desc(dev, "Allwinner A10 DMA Controller") ;
+
+ return (BUS_PROBE_DEFAULT) ;
+}
+
+static int
+a10_dma_attach(device_t dev)
+{
+ uint32_t ind;
+
+ sc = device_get_softc(dev);
+ sc->a10_dma_dev = dev;
+
+ sc->a10_dma_memory_resource = bus_alloc_resource_any(sc->a10_dma_dev, SYS_RES_MEMORY, &sc->a10_dma_mem_rid, RF_ACTIVE);
+ if (sc->a10_dma_memory_resource == NULL) {
+ device_printf(sc->a10_dma_dev, "Cannot allocate DMA memory resource!\n");
+ goto fail;
+ }
+ sc->a10_dma_irq_resource = bus_alloc_resource_any(sc->a10_dma_dev, SYS_RES_IRQ, &sc->a10_dma_irq_rid, RF_ACTIVE | RF_SHAREABLE);
+ if (sc->a10_dma_irq_resource == NULL) {
+ device_printf(sc->a10_dma_dev, "Cannot allocate DMA IRQ resource\n");
+ goto fail;
+ }
+ if (bus_setup_intr(sc->a10_dma_dev, sc->a10_dma_irq_resource, INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, a10_dma_intr,NULL, &sc->a10_dma_intrhand)) {
+ device_printf(sc->a10_dma_dev, "Couldn't setup DMA interrupt handler\n");
+ goto fail;
+ }
+
+ mtx_init(&sc->a10_dma_mtx,device_get_nameunit(sc->a10_dma_dev),"a10_dma",MTX_DEF);
+
+ A10_DMA_WRITE_4(sc, A10_DMA_IRQ_EN, 0);
+ A10_DMA_WRITE_4(sc, A10_DMA_IRQ_PEND_STA, ~0);
+
+ for (ind = 0; ind < NNDMA; ind++) {
+ sc->a10_ndma_channels[ind].ch_index = ind;
+ sc->a10_ndma_channels[ind].ch_a10_dma_intr_args = NULL;
+ sc->a10_ndma_channels[ind].ch_a10_dma_intr_handle = NULL;
+ sc->a10_ndma_channels[ind].ch_offset = A10_NDMA_REG(ind);
+ }
+ for (ind = 0; ind < NDDMA; ind++) {
+ sc->a10_ddma_channels[ind].ch_index = ind;
+ sc->a10_ddma_channels[ind].ch_a10_dma_intr_args = NULL;
+ sc->a10_ddma_channels[ind].ch_a10_dma_intr_handle = NULL;
+ sc->a10_ddma_channels[ind].ch_offset = A10_DDMA_REG(ind);
+ }
+
+ return (0);
+
+ fail:
+ mtx_destroy(&sc->a10_dma_mtx);
+ if (sc->a10_dma_memory_resource != NULL)
+ bus_release_resource(sc->a10_dma_dev, SYS_RES_MEMORY, sc->a10_dma_mem_rid, sc->a10_dma_memory_resource);
+ if (sc->a10_dma_irq_resource != NULL) {
+ bus_teardown_intr(sc->a10_dma_dev, sc->a10_dma_irq_resource,sc->a10_dma_intrhand);
+ bus_release_resource(sc->a10_dma_dev, SYS_RES_IRQ, sc->a10_dma_irq_rid, sc->a10_dma_irq_resource);
+ }
+ return (ENXIO);
+}
+
+static int
+a10_dma_detach(device_t dev)
+{
+ return (EBUSY);
+}
+
+static void
+a10_dma_intr(void *arg)
+{
+ uint32_t status,bit,index;
+ void (*intr)(void*);
+ void *args;
+ status = A10_DMA_READ_4(sc,A10_DMA_IRQ_PEND_STA);
+
+ if (!status)
+ return;
+ A10_DMA_WRITE_4(sc, A10_DMA_IRQ_PEND_STA, status);
+ /* Clear any half transfer interrupts (if present) and acknowledge full transfer interrupts only*/
+ status = status & (0xaaaaaaaa) ;
+ while ((bit = ffs(status)) != 0) {
+ index = ((bit-1)/2)&7;
+ if (bit <= 16) {
+ intr = sc->a10_ndma_channels[index].ch_a10_dma_intr_handle;
+ args = sc->a10_ndma_channels[index].ch_a10_dma_intr_args;
+ if (intr == NULL) {
+ device_printf(sc->a10_dma_dev, "Spurious interrupt, NDMA channel %d not assigned.\n",index);
+ continue;
+ }
+ }
+ else {
+ intr = sc->a10_ddma_channels[index].ch_a10_dma_intr_handle;
+ args = sc->a10_ddma_channels[index].ch_a10_dma_intr_args;
+ if (intr == NULL){
+ device_printf(sc->a10_dma_dev, "Spurious interrupt DDMA channel %d not assigned.\n", index);
+ continue;
+ }
+ }
+ intr(args);
+ }
+
+}
+
+static struct a10_dma_channel *
+a10_dma_alloc_channel(uint32_t type, void (*intr) (void *), void *args)
+{
+ struct a10_dma_channel *list;
+ uint32_t count,index,irqen;
+ if (type == DMA_TYPE_OTHER){
+ list = sc->a10_ndma_channels;
+ count = NNDMA;
+ }
+ else {
+ list = sc->a10_ddma_channels;
+ count = NDDMA;
+ }
+
+ A10_DMA_LOCK(sc);
+ for (index = 0; index < count; index++) {
+ if (list[index].ch_a10_dma_intr_handle == NULL) {
+ list[index].ch_a10_dma_intr_args = args;
+ list[index].ch_a10_dma_intr_handle = intr;
+
+ irqen = A10_DMA_READ_4(sc,A10_DMA_IRQ_EN);
+ if (list[index].ch_type == NDMA)
+ irqen |= A10_DMA_IRQ_NDMA_END(index);
+ else
+ irqen |= A10_DMA_IRQ_DDMA_END(index);
+ A10_DMA_WRITE_4(sc, A10_DMA_IRQ_EN, irqen);
+ break;
+ }
+ }
+ A10_DMA_UNLOCK(sc);
+ if (index == count)
+ return NULL;
+ else
+ return &list[index];
+}
+
+static int
+a10_dma_start_transfer(struct a10_dma_channel *channel, bus_addr_t src, bus_addr_t dest, bus_size_t count)
+{
+ uint32_t config;
+ config = a10_dma_get_config(channel);
+
+ if (channel->ch_type == NDMA) {
+ if (config & A10_NDMA_CTRL_DMA_LOADING)
+ return (EBUSY);
+ A10_DMACH_WRITE_4(channel, A10_NDMA_SRC_ADDR, src);
+ A10_DMACH_WRITE_4(channel, A10_NDMA_DEST_ADDR, dest);
+ A10_DMACH_WRITE_4(channel, A10_NDMA_BC, count);
+
+ config |= A10_NDMA_CTRL_DMA_LOADING;
+ }
+ else {
+ if (config & A10_DDMA_CTRL_DMA_LOADING)
+ return (EBUSY);
+ A10_DMACH_WRITE_4(channel, A10_DDMA_SRC_START_ADDR, src);
+ A10_DMACH_WRITE_4(channel, A10_DDMA_DEST_START_ADDR, dest);
+ A10_DMACH_WRITE_4(channel, A10_DDMA_BC, count);
+ A10_DMACH_WRITE_4(channel, A10_DDMA_PARA,
+ //__SHIFTIN(31, A10_DDMA_PARA_DST_DATA_BLK_SIZ) |
+ __SHIFTIN(7, A10_DDMA_PARA_DST_WAIT_CYC) |
+ //__SHIFTIN(31, A10_DDMA_PARA_SRC_DATA_BLK_SIZ) |
+ __SHIFTIN(7, A10_DDMA_PARA_SRC_WAIT_CYC)) ;
+ config |= A10_DDMA_CTRL_DMA_LOADING;
+ }
+ a10_dma_set_config(channel,config);
+
+ return (0);
+}
+
+/* Do we have to write to the configuration register as well ? */
+static void
+a10_dma_free_channel(struct a10_dma_channel *channel)
+{
+ uint32_t irqen, config;
+
+ if (channel->ch_a10_dma_intr_handle == NULL)
+ return;
+
+ A10_DMA_LOCK(sc);
+ channel->ch_a10_dma_intr_args = NULL;
+ channel->ch_a10_dma_intr_handle = NULL;
+ A10_DMA_UNLOCK(sc);
+
+ /* Disable interrupts and reset the channel. */
+ irqen = A10_DMA_READ_4(sc,A10_DMA_IRQ_EN);
+ config = a10_dma_get_config(channel);
+ if (channel->ch_type == NDMA) {
+ config &= ~(A10_NDMA_CTRL_DMA_LOADING);
+ irqen &= ~(A10_DMA_IRQ_NDMA_END(channel->ch_index));
+ }
+ else {
+ config &= ~(A10_DDMA_CTRL_DMA_LOADING);
+ irqen &= ~(A10_DMA_IRQ_DDMA_END(channel->ch_index));
+ }
+ A10_DMA_WRITE_4(sc, A10_DMA_IRQ_EN, irqen);
+ a10_dma_set_config(channel, config);
+}
+
+static void
+a10_dma_set_config(struct a10_dma_channel *channel, uint32_t config)
+{
+ if (channel->ch_type == NDMA)
+ A10_DMACH_WRITE_4(channel, A10_NDMA_CTRL, config);
+ else
+ A10_DMACH_WRITE_4(channel, A10_DDMA_CTRL, config);
+}
+
+static uint32_t
+a10_dma_get_config(struct a10_dma_channel *channel)
+{
+ if (channel->ch_type == NDMA)
+ return (A10_DMACH_READ_4(channel, A10_NDMA_CTRL));
+ else
+ return (A10_DMACH_READ_4(channel, A10_DDMA_CTRL));
+}
+
+static void
+a10_dma_halt_transfer(struct a10_dma_channel *channel)
+{
+ uint32_t config = a10_dma_get_config(channel);
+ if (channel->ch_type == NDMA)
+ config &= ~A10_NDMA_CTRL_DMA_LOADING;
+ else
+ config &= ~A10_DDMA_CTRL_DMA_LOADING;
+ a10_dma_set_config(channel, config);
+
+}
+
Added: soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h Wed Jul 1 09:58:26 2015 (r287803)
@@ -0,0 +1,168 @@
+/*-
+ * Copyright (c) 2015 Pratik Singhal
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _A10_DMA_H
+#define _A10_DMA_H
+
+#define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
+#define __BIT(__n) (((__n) == 32) ? 0 : ((uint32_t)1 << (__n)))
+#define __BITS(__m, __n) \
+ ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
+#define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
+
+/* Module base address. */
+#define DMA (0x10C02000)
+
+#define NNDMA 8
+#define NDDMA 8
+
+#define A10_DMA_IRQ_EN 0x0000
+#define A10_DMA_IRQ_PEND_STA 0x0004
+#define A10_NDMA_AUTO_GATE 0x0008
+#define A10_NDMA_REG(n) (0x100+0x20*(n))
+#define A10_NDMA_CTRL 0x0000
+#define A10_NDMA_SRC_ADDR 0x0004
+#define A10_NDMA_DEST_ADDR 0x0008
+#define A10_NDMA_BC 0x000c
+
+#define A10_DDMA(n) (0x300+0x20*(n))
+#define A10_DDMA_REG(n) (0x300+0x20*(n))
+#define A10_DDMA_CTRL 0x0000
+#define A10_DDMA_SRC_START_ADDR 0x0004
+#define A10_DDMA_DEST_START_ADDR 0x0008
+#define A10_DDMA_BC 0x000c
+#define A10_DDMA_PARA 0x0018
+
+#define A10_DMA_IRQ_HF_MASK 0x55555555
+#define A10_DMA_IRQ_DDMA __BITS(31,16)
+#define A10_DMA_IRQ_DDMA_END(n) __BIT(17+2*(n))
+#define A10_DMA_IRQ_DDMA_HF(n) __BIT(16+2*(n))
+#define A10_DMA_IRQ_NDMA __BITS(15,0)
+#define A10_DMA_IRQ_NDMA_END(n) __BIT(1+2*(n))
+#define A10_DMA_IRQ_NDMA_HF(n) __BIT(0+2*(n))
+
+#define A10_NDMA_AUTO_GATING_DIS __BIT(16)
+
+#define A10_DMA_CTRL_DST_DATA_WIDTH __BITS(26,25)
+#define A10_DMA_CTRL_DATA_WIDTH_8 0
+#define A10_DMA_CTRL_DATA_WIDTH_16 1
+#define A10_DMA_CTRL_DATA_WIDTH_32 2
+#define A10_DMA_CTRL_DST_BURST_LEN __BITS(24,23)
+#define A10_DMA_CTRL_BURST_LEN_1 0
+#define A10_DMA_CTRL_BURST_LEN_4 1
+#define A10_DMA_CTRL_BURST_LEN_8 2
+#define A10_DMA_CTRL_DST_DRQ_TYPE __BITS(20,16)
+#define A10_DMA_CTRL_BC_REMAINING __BIT(15)
+#define A10_DMA_CTRL_SRC_DATA_WIDTH __BITS(10,9)
+#define A10_DMA_CTRL_SRC_BURST_LEN __BITS(8,7)
+#define A10_DMA_CTRL_SRC_DRQ_TYPE __BITS(4,0)
+
+#define A10_NDMA_CTRL_DMA_LOADING __BIT(31)
+#define A10_NDMA_CTRL_DMA_CONTIN_MODE __BIT(30)
+#define A10_NDMA_CTRL_WAIT_STATE_LOG2 __BITS(29,27)
+#define A10_NDMA_CTRL_DST_NON_SECURE __BIT(22)
+#define A10_NDMA_CTRL_DST_ADDR_NOINCR __BIT(21)
+#define A10_NDMA_CTRL_DRQ_IRO 0
+#define A10_NDMA_CTRL_DRQ_IR1 1
+#define A10_NDMA_CTRL_DRQ_SPDIF 2
+#define A10_NDMA_CTRL_DRQ_IISO 3
+#define A10_NDMA_CTRL_DRQ_IIS1 4
+#define A10_NDMA_CTRL_DRQ_AC97 5
+#define A10_NDMA_CTRL_DRQ_IIS2 6
+#define A10_NDMA_CTRL_DRQ_UARTO 8
+#define A10_NDMA_CTRL_DRQ_UART1 9
+#define A10_NDMA_CTRL_DRQ_UART2 10
+#define A10_NDMA_CTRL_DRQ_UART3 11
+#define A10_NDMA_CTRL_DRQ_UART4 12
+#define A10_NDMA_CTRL_DRQ_UART5 13
+#define A10_NDMA_CTRL_DRQ_UART6 14
+#define A10_NDMA_CTRL_DRQ_UART7 15
+#define A10_NDMA_CTRL_DRQ_DDC 16
+#define A10_NDMA_CTRL_DRQ_USB_EP1 17
+#define A10_NDMA_CTRL_DRQ_CODEC 19
+#define A10_NDMA_CTRL_DRQ_SRAM 21
+#define A10_NDMA_CTRL_DRQ_SDRAM 22
+#define A10_NDMA_CTRL_DRQ_TP_AD 23
+#define A10_NDMA_CTRL_DRQ_SPI0 24
+#define A10_NDMA_CTRL_DRQ_SPI1 25
+#define A10_NDMA_CTRL_DRQ_SPI2 26
+#define A10_NDMA_CTRL_DRQ_SPI3 27
+#define A10_NDMA_CTRL_DRQ_USB_EP2 28
+#define A10_NDMA_CTRL_DRQ_USB_EP3 29
+#define A10_NDMA_CTRL_DRQ_USB_EP4 30
+#define A10_NDMA_CTRL_DRQ_USB_EP5 31
+#define A10_NDMA_CTRL_SRC_NON_SECURE __BIT(6)
+#define A10_NDMA_CTRL_SRC_ADDR_NOINCR __BIT(5)
+
+#define A10_NDMA_BC_COUNT __BITS(17,0)
+
+#define A10_DDMA_CTRL_DMA_LOADING __BIT(31)
+#define A10_DDMA_CTRL_BUSY __BIT(30)
+#define A10_DDMA_CTRL_DMA_CONTIN_MODE __BIT(29)
+#define A10_DDMA_CTRL_DST_NON_SECURE __BIT(28)
+#define A10_DDMA_CTRL_DST_ADDR_MODE __BITS(22,21)
+#define A10_DDMA_CTRL_DMA_ADDR_LINEAR 0
+#define A10_DDMA_CTRL_DMA_ADDR_IO 1
+#define A10_DDMA_CTRL_DMA_ADDR_HPAGE 2
+#define A10_DDMA_CTRL_DMA_ADDR_VPAGE 3
+#define A10_DDMA_CTRL_DST_DRQ_TYPE __BITS(20,16)
+#define A10_DDMA_CTRL_DRQ_SRAM 0
+#define A10_DDMA_CTRL_DRQ_SDRAM 1
+#define A10_DDMA_CTRL_DRQ_NFC 3
+#define A10_DDMA_CTRL_DRQ_USB0 4
+#define A10_DDMA_CTRL_DRQ_EMAC_TX 6
+#define A10_DDMA_CTRL_DRQ_EMAC_RX 7
+#define A10_DDMA_CTRL_DRQ_SPI1_TX 8
+#define A10_DDMA_CTRL_DRQ_SPI1_RX 9
+#define A10_DDMA_CTRL_DRQ_SS_TX 10
+#define A10_DDMA_CTRL_DRQ_SS_RX 11
+#define A10_DDMA_CTRL_DRQ_TCON0 14
+#define A10_DDMA_CTRL_DRQ_TCON1 15
+#define A10_DDMA_CTRL_DRQ_MS_TX 23
+#define A10_DDMA_CTRL_DRQ_MS_RX 23
+#define A10_DDMA_CTRL_DRQ_HDMI_AUDIO 24
+#define A10_DDMA_CTRL_DRQ_SPI0_TX 26
+#define A10_DDMA_CTRL_DRQ_SPI0_RX 27
+#define A10_DDMA_CTRL_DRQ_SPI2_TX 28
+#define A10_DDMA_CTRL_DRQ_SPI2_RX 29
+#define A10_DDMA_CTRL_DRQ_SPI3_TX 30
+#define A10_DDMA_CTRL_DRQ_SPI3_RX 31
+#define A10_DDMA_CTRL_SRC_NON_SECURE __BIT(12)
+#define A10_DDMA_CTRL_SRC_ADDR_MODE __BITS(6,5)
+
+#define A10_DDMA_BC_COUNT __BITS(13,0)
+
+#define A10_DDMA_PARA_DST_DATA_BLK_SIZ __BITS(31,24)
+#define A10_DDMA_PARA_DST_WAIT_CYC __BITS(23,16)
+#define A10_DDMA_PARA_SRC_DATA_BLK_SIZ __BITS(15,8)
+#define A10_DDMA_PARA_SRC_WAIT_CYC __BITS(7,0)
+
+/* To be used with alloc function when passing the type arguement.*/
+#define DMA_TYPE_DDMA 0x01
+#define DMA_TYPE_HDMI_AUDIO 0x02
+#define DMA_TYPE_OTHER 0x03
+
+#endif /* _A10_DMA_H */
\ No newline at end of file
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