socsvn commit: r289984 - in soc2015/pratiksinghal/cubie-head/sys/arm: allwinner conf
pratiksinghal at FreeBSD.org
pratiksinghal at FreeBSD.org
Thu Aug 20 20:11:17 UTC 2015
Author: pratiksinghal
Date: Thu Aug 20 20:11:15 2015
New Revision: 289984
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=289984
Log:
NDMA API now working, made changes to header file
Modified:
soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c
soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h
soc2015/pratiksinghal/cubie-head/sys/arm/conf/CUBIEBOARD
Modified: soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c
==============================================================================
--- soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c Thu Aug 20 20:00:51 2015 (r289983)
+++ soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.c Thu Aug 20 20:11:15 2015 (r289984)
@@ -42,44 +42,8 @@
#include "a10_dma.h"
-enum a10_dma_channel_type {
- NDMA,
- DDMA
-} ;
-
-struct a10_dma_channel {
- enum a10_dma_channel_type ch_type;
- uint32_t ch_index;
- void (*ch_a10_dma_intr_handle) (void *);
- void * ch_a10_dma_intr_args;
- bus_size_t ch_offset;
-};
-
-struct a10_dma_softc {
- device_t a10_dma_dev;
- bus_space_tag_t a10_dma_bst;
- bus_space_handle_t a10_dma_bsh;
- struct resource * a10_dma_memory_resource;
- struct resource * a10_dma_irq_resource;
- void* a10_dma_intrhand;
- int a10_dma_mem_rid;
- int a10_dma_irq_rid;
- struct mtx a10_dma_mtx;
- struct a10_dma_channel a10_ndma_channels[NNDMA];
- struct a10_dma_channel a10_ddma_channels[NDDMA];
-} ;
static struct a10_dma_softc *sc;
-static int a10_dma_probe(device_t);
-static int a10_dma_attach(device_t);
-static int a10_dma_detach(device_t);
-static void a10_dma_intr(void *);
-static struct a10_dma_channel * a10_dma_alloc_channel(uint32_t, void (*) (void *), void *);
-static int a10_dma_start_transfer(struct a10_dma_channel *, bus_addr_t, bus_addr_t, bus_size_t);
-static void a10_dma_free_channel(struct a10_dma_channel *);
-static void a10_dma_set_config(struct a10_dma_channel *, uint32_t);
-static uint32_t a10_dma_get_config(struct a10_dma_channel *);
-static void a10_dma_halt(struct a10_dma_channel *);
#define A10_DMA_LOCK(_sc) mtx_lock(&(_sc)->a10_dma_mtx)
#define A10_DMA_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_dma_mtx)
@@ -93,7 +57,7 @@
A10_DMA_WRITE_4(sc, (_reg) + (_sc)->ch_offset, _value)
-static int
+int
a10_dma_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
@@ -105,7 +69,7 @@
return (BUS_PROBE_DEFAULT) ;
}
-static int
+int
a10_dma_attach(device_t dev)
{
uint32_t ind;
@@ -160,13 +124,13 @@
return (ENXIO);
}
-static int
+int
a10_dma_detach(device_t dev)
{
return (EBUSY);
}
-static void
+void
a10_dma_intr(void *arg)
{
uint32_t status,bit,index;
@@ -202,7 +166,7 @@
}
-static struct a10_dma_channel *
+struct a10_dma_channel *
a10_dma_alloc_channel(uint32_t type, void (*intr) (void *), void *args)
{
struct a10_dma_channel *list;
@@ -238,23 +202,23 @@
return &list[index];
}
-static int
+int
a10_dma_start_transfer(struct a10_dma_channel *channel, bus_addr_t src, bus_addr_t dest, bus_size_t count)
{
uint32_t config;
config = a10_dma_get_config(channel);
if (channel->ch_type == NDMA) {
- if (config & A10_NDMA_CTRL_DMA_LOADING)
+ if (config & A10_NDMA_DMA_LOADING)
return (EBUSY);
A10_DMACH_WRITE_4(channel, A10_NDMA_SRC_ADDR, src);
A10_DMACH_WRITE_4(channel, A10_NDMA_DEST_ADDR, dest);
A10_DMACH_WRITE_4(channel, A10_NDMA_BC, count);
- config |= A10_NDMA_CTRL_DMA_LOADING;
+ config |= A10_NDMA_DMA_LOADING;
}
else {
- if (config & A10_DDMA_CTRL_DMA_LOADING)
+ if (config & A10_DDMA_DMA_LOADING)
return (EBUSY);
A10_DMACH_WRITE_4(channel, A10_DDMA_SRC_START_ADDR, src);
A10_DMACH_WRITE_4(channel, A10_DDMA_DEST_START_ADDR, dest);
@@ -264,7 +228,7 @@
__SHIFTIN(7, A10_DDMA_PARA_DST_WAIT_CYC) |
//__SHIFTIN(31, A10_DDMA_PARA_SRC_DATA_BLK_SIZ) |
__SHIFTIN(7, A10_DDMA_PARA_SRC_WAIT_CYC)) ;
- config |= A10_DDMA_CTRL_DMA_LOADING;
+ config |= A10_DDMA_DMA_LOADING;
}
a10_dma_set_config(channel,config);
@@ -272,7 +236,7 @@
}
/* Do we have to write to the configuration register as well ? */
-static void
+void
a10_dma_free_channel(struct a10_dma_channel *channel)
{
uint32_t irqen, config;
@@ -289,18 +253,18 @@
irqen = A10_DMA_READ_4(sc,A10_DMA_IRQ_EN);
config = a10_dma_get_config(channel);
if (channel->ch_type == NDMA) {
- config &= ~(A10_NDMA_CTRL_DMA_LOADING);
+ config &= ~(A10_NDMA_DMA_LOADING);
irqen &= ~(A10_DMA_IRQ_NDMA_END(channel->ch_index));
}
else {
- config &= ~(A10_DDMA_CTRL_DMA_LOADING);
+ config &= ~(A10_DDMA_DMA_LOADING);
irqen &= ~(A10_DMA_IRQ_DDMA_END(channel->ch_index));
}
A10_DMA_WRITE_4(sc, A10_DMA_IRQ_EN, irqen);
a10_dma_set_config(channel, config);
}
-static void
+void
a10_dma_set_config(struct a10_dma_channel *channel, uint32_t config)
{
if (channel->ch_type == NDMA)
@@ -309,7 +273,7 @@
A10_DMACH_WRITE_4(channel, A10_DDMA_CTRL, config);
}
-static uint32_t
+uint32_t
a10_dma_get_config(struct a10_dma_channel *channel)
{
if (channel->ch_type == NDMA)
@@ -318,14 +282,14 @@
return (A10_DMACH_READ_4(channel, A10_DDMA_CTRL));
}
-static void
+void
a10_dma_halt_transfer(struct a10_dma_channel *channel)
{
uint32_t config = a10_dma_get_config(channel);
if (channel->ch_type == NDMA)
- config &= ~A10_NDMA_CTRL_DMA_LOADING;
+ config &= ~A10_NDMA_DMA_LOADING;
else
- config &= ~A10_DDMA_CTRL_DMA_LOADING;
+ config &= ~A10_DDMA_DMA_LOADING;
a10_dma_set_config(channel, config);
}
Modified: soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h
==============================================================================
--- soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h Thu Aug 20 20:00:51 2015 (r289983)
+++ soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_dma.h Thu Aug 20 20:11:15 2015 (r289984)
@@ -36,9 +36,11 @@
/* Module base address. */
#define DMA (0x10C02000)
+/* No of DMA channels available */
#define NNDMA 8
#define NDDMA 8
+/* Registers provided by DMA controller */
#define A10_DMA_IRQ_EN 0x0000
#define A10_DMA_IRQ_PEND_STA 0x0004
#define A10_NDMA_AUTO_GATE 0x0008
@@ -47,7 +49,6 @@
#define A10_NDMA_SRC_ADDR 0x0004
#define A10_NDMA_DEST_ADDR 0x0008
#define A10_NDMA_BC 0x000c
-
#define A10_DDMA(n) (0x300+0x20*(n))
#define A10_DDMA_REG(n) (0x300+0x20*(n))
#define A10_DDMA_CTRL 0x0000
@@ -56,6 +57,7 @@
#define A10_DDMA_BC 0x000c
#define A10_DDMA_PARA 0x0018
+/* Interrupt masking values */
#define A10_DMA_IRQ_HF_MASK 0x55555555
#define A10_DMA_IRQ_DDMA __BITS(31,16)
#define A10_DMA_IRQ_DDMA_END(n) __BIT(17+2*(n))
@@ -66,92 +68,122 @@
#define A10_NDMA_AUTO_GATING_DIS __BIT(16)
-#define A10_DMA_CTRL_DST_DATA_WIDTH __BITS(26,25)
-#define A10_DMA_CTRL_DATA_WIDTH_8 0
-#define A10_DMA_CTRL_DATA_WIDTH_16 1
-#define A10_DMA_CTRL_DATA_WIDTH_32 2
-#define A10_DMA_CTRL_DST_BURST_LEN __BITS(24,23)
-#define A10_DMA_CTRL_BURST_LEN_1 0
-#define A10_DMA_CTRL_BURST_LEN_4 1
-#define A10_DMA_CTRL_BURST_LEN_8 2
-#define A10_DMA_CTRL_DST_DRQ_TYPE __BITS(20,16)
-#define A10_DMA_CTRL_BC_REMAINING __BIT(15)
-#define A10_DMA_CTRL_SRC_DATA_WIDTH __BITS(10,9)
-#define A10_DMA_CTRL_SRC_BURST_LEN __BITS(8,7)
-#define A10_DMA_CTRL_SRC_DRQ_TYPE __BITS(4,0)
-
-#define A10_NDMA_CTRL_DMA_LOADING __BIT(31)
-#define A10_NDMA_CTRL_DMA_CONTIN_MODE __BIT(30)
-#define A10_NDMA_CTRL_WAIT_STATE_LOG2 __BITS(29,27)
-#define A10_NDMA_CTRL_DST_NON_SECURE __BIT(22)
-#define A10_NDMA_CTRL_DST_ADDR_NOINCR __BIT(21)
-#define A10_NDMA_CTRL_DRQ_IRO 0
-#define A10_NDMA_CTRL_DRQ_IR1 1
-#define A10_NDMA_CTRL_DRQ_SPDIF 2
-#define A10_NDMA_CTRL_DRQ_IISO 3
-#define A10_NDMA_CTRL_DRQ_IIS1 4
-#define A10_NDMA_CTRL_DRQ_AC97 5
-#define A10_NDMA_CTRL_DRQ_IIS2 6
-#define A10_NDMA_CTRL_DRQ_UARTO 8
-#define A10_NDMA_CTRL_DRQ_UART1 9
-#define A10_NDMA_CTRL_DRQ_UART2 10
-#define A10_NDMA_CTRL_DRQ_UART3 11
-#define A10_NDMA_CTRL_DRQ_UART4 12
-#define A10_NDMA_CTRL_DRQ_UART5 13
-#define A10_NDMA_CTRL_DRQ_UART6 14
-#define A10_NDMA_CTRL_DRQ_UART7 15
-#define A10_NDMA_CTRL_DRQ_DDC 16
-#define A10_NDMA_CTRL_DRQ_USB_EP1 17
-#define A10_NDMA_CTRL_DRQ_CODEC 19
-#define A10_NDMA_CTRL_DRQ_SRAM 21
-#define A10_NDMA_CTRL_DRQ_SDRAM 22
-#define A10_NDMA_CTRL_DRQ_TP_AD 23
-#define A10_NDMA_CTRL_DRQ_SPI0 24
-#define A10_NDMA_CTRL_DRQ_SPI1 25
-#define A10_NDMA_CTRL_DRQ_SPI2 26
-#define A10_NDMA_CTRL_DRQ_SPI3 27
-#define A10_NDMA_CTRL_DRQ_USB_EP2 28
-#define A10_NDMA_CTRL_DRQ_USB_EP3 29
-#define A10_NDMA_CTRL_DRQ_USB_EP4 30
-#define A10_NDMA_CTRL_DRQ_USB_EP5 31
-#define A10_NDMA_CTRL_SRC_NON_SECURE __BIT(6)
-#define A10_NDMA_CTRL_SRC_ADDR_NOINCR __BIT(5)
-
-#define A10_NDMA_BC_COUNT __BITS(17,0)
-
-#define A10_DDMA_CTRL_DMA_LOADING __BIT(31)
-#define A10_DDMA_CTRL_BUSY __BIT(30)
-#define A10_DDMA_CTRL_DMA_CONTIN_MODE __BIT(29)
-#define A10_DDMA_CTRL_DST_NON_SECURE __BIT(28)
-#define A10_DDMA_CTRL_DST_ADDR_MODE __BITS(22,21)
-#define A10_DDMA_CTRL_DMA_ADDR_LINEAR 0
-#define A10_DDMA_CTRL_DMA_ADDR_IO 1
-#define A10_DDMA_CTRL_DMA_ADDR_HPAGE 2
-#define A10_DDMA_CTRL_DMA_ADDR_VPAGE 3
-#define A10_DDMA_CTRL_DST_DRQ_TYPE __BITS(20,16)
-#define A10_DDMA_CTRL_DRQ_SRAM 0
-#define A10_DDMA_CTRL_DRQ_SDRAM 1
-#define A10_DDMA_CTRL_DRQ_NFC 3
-#define A10_DDMA_CTRL_DRQ_USB0 4
-#define A10_DDMA_CTRL_DRQ_EMAC_TX 6
-#define A10_DDMA_CTRL_DRQ_EMAC_RX 7
-#define A10_DDMA_CTRL_DRQ_SPI1_TX 8
-#define A10_DDMA_CTRL_DRQ_SPI1_RX 9
-#define A10_DDMA_CTRL_DRQ_SS_TX 10
-#define A10_DDMA_CTRL_DRQ_SS_RX 11
-#define A10_DDMA_CTRL_DRQ_TCON0 14
-#define A10_DDMA_CTRL_DRQ_TCON1 15
-#define A10_DDMA_CTRL_DRQ_MS_TX 23
-#define A10_DDMA_CTRL_DRQ_MS_RX 23
-#define A10_DDMA_CTRL_DRQ_HDMI_AUDIO 24
-#define A10_DDMA_CTRL_DRQ_SPI0_TX 26
-#define A10_DDMA_CTRL_DRQ_SPI0_RX 27
-#define A10_DDMA_CTRL_DRQ_SPI2_TX 28
-#define A10_DDMA_CTRL_DRQ_SPI2_RX 29
-#define A10_DDMA_CTRL_DRQ_SPI3_TX 30
-#define A10_DDMA_CTRL_DRQ_SPI3_RX 31
-#define A10_DDMA_CTRL_SRC_NON_SECURE __BIT(12)
-#define A10_DDMA_CTRL_SRC_ADDR_MODE __BITS(6,5)
+/* Normal DMA connfiguration values */
+#define A10_NDMA_DMA_LOADING __BIT(31)
+#define A10_NDMA_DMA_CONTIN_MODE __BIT(30)
+#define A10_NDMA_WAIT_STATE(n) (n << 27)
+#define A10_NDMA_DST_NON_SECURE __BIT(22)
+#define A10_NDMA_DST_ADDR_NOINCR __BIT(21)
+#define A10_NDMA_DEST_8 (0 << 25)
+#define A10_NDMA_DEST_16 (1 << 25)
+#define A10_NDMA_DEST_32 (2 << 25)
+#define A10_NDMA_DEST_BST_1 (0 << 23)
+#define A10_NDMA_DEST_BST_4 (1 << 23)
+#define A10_NDMA_DEST_BST_8 (2 << 23)
+#define A10_NDMA_DEST_NON_SEC (1 << 22)
+#define A10_NDMA_DEST_ADDR_NCHANGE (1 << 21)
+#define A10_NDMA_DEST_IRO (0 << 16)
+#define A10_NDMA_DEST_IR1 (1 << 16)
+#define A10_NDMA_DEST_SPDIF (2 << 16)
+#define A10_NDMA_DEST_IISO (3 << 16)
+#define A10_NDMA_DEST_IIS1 (4 << 16)
+#define A10_NDMA_DEST_AC97 (5 << 16)
+#define A10_NDMA_DEST_IIS2 (6 << 16)
+#define A10_NDMA_DEST_UARTO (8 << 16)
+#define A10_NDMA_DEST_UART1 (9 << 16)
+#define A10_NDMA_DEST_UART2 (10 << 16)
+#define A10_NDMA_DEST_UART3 (11 << 16)
+#define A10_NDMA_DEST_UART4 (12 << 16)
+#define A10_NDMA_DEST_UART5 (13 << 16)
+#define A10_NDMA_DEST_UART6 (14 << 16)
+#define A10_NDMA_DEST_UART7 (15 << 16)
+#define A10_NDMA_DEST_DDC (16 << 16)
+#define A10_NDMA_DEST_USB_EP1 (17 << 16)
+#define A10_NDMA_DEST_CODEC (19 << 16)
+#define A10_NDMA_DEST_SRAM (21 << 16)
+#define A10_NDMA_DEST_SDRAM (22 << 16)
+#define A10_NDMA_DEST_TP_AD (23 << 16)
+#define A10_NDMA_DEST_SPI0 (24 << 16)
+#define A10_NDMA_DEST_SPI1 (25 << 16)
+#define A10_NDMA_DEST_SPI2 (26 << 16)
+#define A10_NDMA_DEST_SPI3 (27 << 16)
+#define A10_NDMA_DEST_USB_EP2 (28 << 16)
+#define A10_NDMA_DEST_USB_EP3 (29 << 16)
+#define A10_NDMA_DEST_USB_EP4 (30 << 16)
+#define A10_NDMA_DEST_USB_EP5 (31 << 16)
+#define A10_NDMA_BC_REMAIN (1 << 15)
+#define A10_NDMA_SRC_8 (0 << 9)
+#define A10_NDMA_SRC_16 (1 << 9)
+#define A10_NDMA_SRC_32 (2 << 9)
+#define A10_NDMA_SRC_BST_1 (0 << 7)
+#define A10_NDMA_SRC_BST_4 (1 << 7)
+#define A10_NDMA_SRC_BST_8 (2 << 7)
+#define A10_NDMA_SRC_NON_SECURE (1 << 6)
+#define A10_NDMA_SRC_ADDR_NCHANGE (1 << 5)
+#define A10_NDMA_SRC_IRO 0
+#define A10_NDMA_SRC_IR1 1
+#define A10_NDMA_SRC_SPDIF 2
+#define A10_NDMA_SRC_IISO 3
+#define A10_NDMA_SRC_IIS1 4
+#define A10_NDMA_SRC_AC97 5
+#define A10_NDMA_SRC_IIS2 6
+#define A10_NDMA_SRC_UARTO 8
+#define A10_NDMA_SRC_UART1 9
+#define A10_NDMA_SRC_UART2 10
+#define A10_NDMA_SRC_UART3 11
+#define A10_NDMA_SRC_UART4 12
+#define A10_NDMA_SRC_UART5 13
+#define A10_NDMA_SRC_UART6 14
+#define A10_NDMA_SRC_UART7 15
+#define A10_NDMA_SRC_DDC 16
+#define A10_NDMA_SRC_USB_EP1 17
+#define A10_NDMA_SRC_CODEC 19
+#define A10_NDMA_SRC_SRAM 21
+#define A10_NDMA_SRC_SDRAM 22
+#define A10_NDMA_SRC_TP_AD 23
+#define A10_NDMA_SRC_SPI0 24
+#define A10_NDMA_SRC_SPI1 25
+#define A10_NDMA_SRC_SPI2 26
+#define A10_NDMA_SRC_SPI3 27
+#define A10_NDMA_SRC_USB_EP2 28
+#define A10_NDMA_SRC_USB_EP3 29
+#define A10_NDMA_SRC_USB_EP4 30
+#define A10_NDMA_SRC_USB_EP5 31
+
+
+#define A10_DDMA_DMA_LOADING __BIT(31)
+#define A10_DDMA_BUSY __BIT(30)
+#define A10_DDMA_DMA_CONTIN_MODE __BIT(29)
+#define A10_DDMA_DST_NON_SECURE __BIT(28)
+#define A10_DDMA_DST_ADDR_MODE __BITS(22,21)
+#define A10_DDMA_DMA_ADDR_LINEAR 0
+#define A10_DDMA_DMA_ADDR_IO 1
+#define A10_DDMA_DMA_ADDR_HPAGE 2
+#define A10_DDMA_DMA_ADDR_VPAGE 3
+#define A10_DDMA_DST_DRQ_TYPE __BITS(20,16)
+#define A10_DDMA_DRQ_SRAM 0
+#define A10_DDMA_DRQ_SDRAM 1
+#define A10_DDMA_DRQ_NFC 3
+#define A10_DDMA_DRQ_USB0 4
+#define A10_DDMA_DRQ_EMAC_TX 6
+#define A10_DDMA_DRQ_EMAC_RX 7
+#define A10_DDMA_DRQ_SPI1_TX 8
+#define A10_DDMA_DRQ_SPI1_RX 9
+#define A10_DDMA_DRQ_SS_TX 10
+#define A10_DDMA_DRQ_SS_RX 11
+#define A10_DDMA_DRQ_TCON0 14
+#define A10_DDMA_DRQ_TCON1 15
+#define A10_DDMA_DRQ_MS_TX 23
+#define A10_DDMA_DRQ_MS_RX 23
+#define A10_DDMA_DRQ_HDMI_AUDIO 24
+#define A10_DDMA_DRQ_SPI0_TX 26
+#define A10_DDMA_DRQ_SPI0_RX 27
+#define A10_DDMA_DRQ_SPI2_TX 28
+#define A10_DDMA_DRQ_SPI2_RX 29
+#define A10_DDMA_DRQ_SPI3_TX 30
+#define A10_DDMA_DRQ_SPI3_RX 31
+#define A10_DDMA_SRC_NON_SECURE __BIT(12)
+#define A10_DDMA_SRC_ADDR_MODE __BITS(6,5)
#define A10_DDMA_BC_COUNT __BITS(13,0)
@@ -165,4 +197,42 @@
#define DMA_TYPE_HDMI_AUDIO 0x02
#define DMA_TYPE_OTHER 0x03
-#endif /* _A10_DMA_H */
\ No newline at end of file
+enum a10_dma_channel_type {
+ NDMA,
+ DDMA
+} ;
+
+struct a10_dma_channel {
+ enum a10_dma_channel_type ch_type;
+ uint32_t ch_index;
+ void (*ch_a10_dma_intr_handle) (void *);
+ void * ch_a10_dma_intr_args;
+ bus_size_t ch_offset;
+};
+
+struct a10_dma_softc {
+ device_t a10_dma_dev;
+ bus_space_tag_t a10_dma_bst;
+ bus_space_handle_t a10_dma_bsh;
+ struct resource * a10_dma_memory_resource;
+ struct resource * a10_dma_irq_resource;
+ void* a10_dma_intrhand;
+ int a10_dma_mem_rid;
+ int a10_dma_irq_rid;
+ struct mtx a10_dma_mtx;
+ struct a10_dma_channel a10_ndma_channels[NNDMA];
+ struct a10_dma_channel a10_ddma_channels[NDDMA];
+} ;
+
+int a10_dma_probe(device_t);
+int a10_dma_attach(device_t);
+int a10_dma_detach(device_t);
+void a10_dma_intr(void *);
+struct a10_dma_channel * a10_dma_alloc_channel(uint32_t, void (*) (void *), void *);
+int a10_dma_start_transfer(struct a10_dma_channel *, bus_addr_t, bus_addr_t, bus_size_t);
+void a10_dma_free_channel(struct a10_dma_channel *);
+void a10_dma_set_config(struct a10_dma_channel *, uint32_t);
+uint32_t a10_dma_get_config(struct a10_dma_channel *);
+void a10_dma_halt_transfer(struct a10_dma_channel *);
+
+#endif /* _A10_DMA_H */
Modified: soc2015/pratiksinghal/cubie-head/sys/arm/conf/CUBIEBOARD
==============================================================================
--- soc2015/pratiksinghal/cubie-head/sys/arm/conf/CUBIEBOARD Thu Aug 20 20:00:51 2015 (r289983)
+++ soc2015/pratiksinghal/cubie-head/sys/arm/conf/CUBIEBOARD Thu Aug 20 20:11:15 2015 (r289984)
@@ -101,7 +101,7 @@
device emac
#DMA controller
-#device dma
+device dma
# USB ethernet support, requires miibus
device miibus
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