socsvn commit: r237265 - in soc2012/aleek/beaglexm-armv6/sys:
arm/arm arm/ti arm/ti/am37x boot/fdt/dts
aleek at FreeBSD.org
aleek at FreeBSD.org
Thu Jun 7 15:32:57 UTC 2012
Author: aleek
Date: Thu Jun 7 15:32:54 2012
New Revision: 237265
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=237265
Log:
early uart is extended. Working on bug with pmap
Added:
soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c
soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.h
Modified:
soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S
soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/files.am37x
soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c
soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S Thu Jun 7 15:08:05 2012 (r237264)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S Thu Jun 7 15:32:54 2012 (r237265)
@@ -1,8 +1,5 @@
/*-
- * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
- * All rights reserved.
- *
- * Developed by Semihalf.
+ * Copyright (c) 2010 Per Odlund <per.odlund at armagedon.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -12,264 +9,150 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. Neither the name of MARVELL nor the names of contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*/
-#include <machine/asm.h>
-__FBSDID("$FreeBSD$");
+/* ARMv7 assembly functions for manipulating caches and other core functions.
+ * Based on cpufuncs for v6 and xscale.
+ */
-.Lcoherency_level:
- .word _C_LABEL(arm_cache_loc)
-.Lcache_type:
- .word _C_LABEL(arm_cache_type)
-.Lway_mask:
- .word 0x3ff
-.Lmax_index:
- .word 0x7fff
-.Lpage_mask:
- .word 0xfff
-
-#define PT_NOS (1 << 5)
-#define PT_S (1 << 1)
-#define PT_INNER_NC 0
-#define PT_INNER_WT (1 << 0)
-#define PT_INNER_WB ((1 << 0) | (1 << 6))
-#define PT_INNER_WBWA (1 << 6)
-#define PT_OUTER_NC 0
-#define PT_OUTER_WT (2 << 3)
-#define PT_OUTER_WB (3 << 3)
-#define PT_OUTER_WBWA (1 << 3)
-
-#ifdef SMP
-#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS)
-#else
-#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT)
-#endif
-ENTRY(armv7_setttb)
- stmdb sp!, {r0, lr}
- bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
- ldmia sp!, {r0, lr}
- dsb
-
- orr r0, r0, #PT_ATTR
- mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
- dsb
- isb
- RET
-
-ENTRY(armv7_tlb_flushID)
- dsb
-#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0
-#else
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
-#endif
- mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
- dsb
- isb
- mov pc, lr
+#include <machine/asm.h>
-ENTRY(armv7_tlb_flushID_SE)
- ldr r1, .Lpage_mask
- bic r0, r0, r1
-#ifdef SMP
- mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry */
-#else
- mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */
-#endif
- mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
- dsb
- isb
- mov pc, lr
-
-/* Based on algorithm from ARM Architecture Reference Manual */
-ENTRY(armv7_dcache_wbinv_all)
- stmdb sp!, {r4, r5, r6, r7, r8, r9}
-
- /* Get cache level */
- ldr r0, .Lcoherency_level
- ldr r3, [r0]
- cmp r3, #0
- beq Finished
- /* For each cache level */
- mov r8, #0
-Loop1:
- /* Get cache type for given level */
- mov r2, r8, lsl #2
- add r2, r2, r2
- ldr r0, .Lcache_type
- ldr r1, [r0, r2]
-
- /* Get line size */
- and r2, r1, #7
- add r2, r2, #4
-
- /* Get number of ways */
- ldr r4, .Lway_mask
- ands r4, r4, r1, lsr #3
- clz r5, r4
-
- /* Get max index */
- ldr r7, .Lmax_index
- ands r7, r7, r1, lsr #13
-Loop2:
- mov r9, r4
-Loop3:
- mov r6, r8, lsl #1
- orr r6, r6, r9, lsl r5
- orr r6, r6, r7, lsl r2
-
- /* Clean and invalidate data cache by way/index */
- mcr p15, 0, r6, c7, c14, 2
- subs r9, r9, #1
- bge Loop3
- subs r7, r7, #1
- bge Loop2
-Skip:
- add r8, r8, #1
- cmp r3, r8
- bne Loop1
-Finished:
- dsb
- ldmia sp!, {r4, r5, r6, r7, r8, r9}
- RET
-
-ENTRY(armv7_idcache_wbinv_all)
- stmdb sp!, {lr}
- bl armv7_dcache_wbinv_all
- mcr p15, 0, r0, c7, c5, 0 /* Invalidate all I caches to PoU (ICIALLU) */
- dsb
- isb
- ldmia sp!, {lr}
+#define entrysize #32
+
+ENTRY(armv7_cpu_sleep)
+ tst r0, #0x00000000 /* shouldn't sleep 0 */
RET
-/* XXX Temporary set it to 32 for MV cores, however this value should be
- * get from Cache Type register
- */
-.Larmv7_line_size:
- .word 32
-ENTRY(armv7_dcache_wb_range)
- ldr ip, .Larmv7_line_size
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larmv7_wb_next:
- mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bhi .Larmv7_wb_next
- dsb /* data synchronization barrier */
+ENTRY(armv7_wait)
+ mrc p15, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
+ add r0, r0, #0 /* a stall */
RET
-ENTRY(armv7_dcache_wbinv_range)
- ldr ip, .Larmv7_line_size
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larmv7_wbinv_next:
- mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bhi .Larmv7_wbinv_next
- dsb /* data synchronization barrier */
+
+ENTRY(armv7_context_switch)
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
+ mcr p15, 0, r0, c8, c7, 0 /* flush the I+D */
RET
-/*
- * Note, we must not invalidate everything. If the range is too big we
- * must use wb-inv of the entire cache.
- */
-ENTRY(armv7_dcache_inv_range)
- ldr ip, .Larmv7_line_size
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larmv7_inv_next:
- mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bhi .Larmv7_inv_next
- dsb /* data synchronization barrier */
+
+ENTRY(armv7_tlb_flushID_SE)
+ mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
+ mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
-ENTRY(armv7_idcache_wbinv_range)
- ldr ip, .Larmv7_line_size
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larmv7_id_wbinv_next:
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bhi .Larmv7_id_wbinv_next
- isb /* instruction synchronization barrier */
- dsb /* data synchronization barrier */
+
+
+ENTRY(armv7_setttb)
+ stmdb sp!, {r0, lr}
+ bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
+ ldmia sp!, {r0, lr}
+
+ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+
RET
+/* Cache operations. */
+
+/* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */
ENTRY_NP(armv7_icache_sync_range)
- ldr ip, .Larmv7_line_size
-.Larmv7_sync_next:
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bhi .Larmv7_sync_next
- isb /* instruction synchronization barrier */
- dsb /* data synchronization barrier */
+1:
+ mcr p15, 0, r0, c7, c5, 1 /* invalidate the I-Cache line */
+ mcr p15, 0, r0, c7, c10, 1 /* wb the D-Cache line */
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
RET
-ENTRY(armv7_cpu_sleep)
- dsb /* data synchronization barrier */
- wfi /* wait for interrupt */
+
+/* LINTSTUB: void armv7_icache_sync_all(void); */
+ENTRY_NP(armv7_icache_sync_all)
+ /*
+ * We assume that the code here can never be out of sync with the
+ * dcache, so that we can safely flush the Icache and fall through
+ * into the Dcache cleaning code.
+ */
+ stmdb sp!, {r0, lr}
+ bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
+ ldmia sp!, {r0, lr}
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
RET
-ENTRY(armv7_context_switch)
- dsb
- orr r0, r0, #PT_ATTR
-
- mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
- dsb
- isb
+
+/* LINTSTUB: armv7_dcache_wb_range(vaddr_t, vsize_t); */
+ENTRY(armv7_dcache_wb_range)
+1:
+ mcr p15, 0, r0, c7, c10, 1 /* wb the D-Cache */
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
RET
-ENTRY(armv7_drain_writebuf)
- dsb
+
+/* LINTSTUB: void armv7_dcache_wbinv_range(vaddr_t, vsize_t); */
+ENTRY(armv7_dcache_wbinv_range)
+1:
+ mcr p15, 0, r0, c7, c14, 1 /* wb and inv the D-Cache line */
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
RET
-ENTRY(armv7_sev)
- dsb
- sev
- nop
+/* * LINTSTUB: void armv7_dcache_inv_range(vaddr_t, vsize_t); */
+ENTRY(armv7_dcache_inv_range)
+1:
+ mcr p15, 0, r0, c7, c6, 1 /* invalidate the D-Cache line */
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
RET
-ENTRY(armv7_auxctrl)
- mrc p15, 0, r2, c1, c0, 1
- bic r3, r2, r0 /* Clear bits */
- eor r3, r3, r1 /* XOR bits */
- teq r2, r3
- mcrne p15, 0, r3, c1, c0, 1
- mov r0, r2
+ENTRY(armv7_idcache_wbinv_range)
+1:
+ mcr p15, 0, r0, c7, c5, 1 /* invalidate the I-Cache line */
+ mcr p15, 0, r0, c7, c14, 1 /* wb and inv the D-Cache line */
+ add r0, r0, entrysize
+ subs r1, r1, entrysize
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
RET
+
+
+ENTRY_NP(armv7_idcache_wbinv_all)
+ /*
+ * We assume that the code here can never be out of sync with the
+ * dcache, so that we can safely flush the Icache and fall through
+ * into the Dcache purging code.
+ */
+ mcr p15, 0, r0, c7, c5, 0
+ b _C_LABEL(armv7_dcache_wbinv_all)
+
+
+/*
+ * armv7_dcache_wbinv_all is in cpufunc.c. It's really too long to
+ * write in assembler.
+ */
Added: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c Thu Jun 7 15:32:54 2012 (r237265)
@@ -0,0 +1,200 @@
+/*-
+ * Copyright (c) 2009 Guillaume Ballet
+ * Copyright (c) 2012 Aleksander Dutkowski
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Debugging functions for early uart for omap3530 and am37x TI SoC's
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <machine/pcb.h>
+#include <machine/machdep.h>
+#include <machine/undefined.h>
+#include <machine/pte.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <sys/kdb.h>
+#include <arm/include/stdarg.h>
+
+#include <arm/ti/am37x/am37x_early_uart.h>
+
+
+
+void
+arm_early_putc( char c )
+{
+ volatile uint32_t *uart = (volatile uint32_t *)0x49020000;
+ volatile uint32_t *uart_lsr = (volatile uint32_t *)0x49020014;
+
+ while ((*uart_lsr & 0x20) == 0);
+ *uart = c;
+
+ if( c == '\n' )
+ {
+ while ((*uart_lsr & 0x20) == 0);
+ *uart = '\r';
+ }
+}
+
+void
+arm_early_puts(unsigned char *str)
+{
+ do {
+ arm_early_putc(*str);
+ } while (*++str != '\0');
+}
+
+void
+eprintf(const char *fmt,...)
+{
+ va_list ap;
+ const char *hex = "0123456789abcdef";
+ char buf[10];
+ char *s;
+ unsigned u;
+ int c;
+
+ va_start(ap, fmt);
+ while ((c = *fmt++)) {
+ if (c == '%') {
+ c = *fmt++;
+ switch (c) {
+ case 'c':
+ arm_early_putc(va_arg(ap, int));
+ continue;
+ case 's':
+ for (s = va_arg(ap, char *); *s; s++)
+ arm_early_putc(*s);
+ continue;
+ case 'd': /* A lie, always prints unsigned */
+ case 'u':
+ u = va_arg(ap, unsigned);
+ s = buf;
+ do
+ *s++ = '0' + u % 10U;
+ while (u /= 10U);
+ dumpbuf:;
+ while (--s >= buf)
+ arm_early_putc(*s);
+ continue;
+ case 'x':
+ u = va_arg(ap, unsigned);
+ s = buf;
+ do
+ *s++ = hex[u & 0xfu];
+ while (u >>= 4);
+ goto dumpbuf;
+ }
+ }
+ arm_early_putc(c);
+ }
+ va_end(ap);
+
+ return;
+}
+
+void
+dump_l2pagetable(uint32_t pta, uint32_t l1)
+{
+ int i;
+ volatile uint32_t *pt = (volatile uint32_t*)pta;
+
+ for (i=0; i<256;i++) {
+ switch (pt[i] & 0x3) {
+ case 1:
+ eprintf("0x%x -> 0x%x 64K ",(i<<12) | l1,
+ pt[i]&0xFFFF0000);
+ eprintf("l2pt[0x%x]=0x%x ",i, pt[i]);
+ eprintf("s=%u ", (pt[i]>>10) &0x1);
+ eprintf("apx=%u ", (pt[i]>> 9) &0x1);
+ eprintf("tex=%u ", (pt[i]>>12) &0x7);
+ eprintf("ap=%u ", (pt[i]>> 4) &0x3);
+ eprintf("c=%u ", (pt[i]>> 3) &0x1);
+ eprintf("b=%u\n", (pt[i]>> 2) &0x1);
+ break;
+ case 2:
+ case 3:
+ eprintf("0x%x -> 0x%x 4K ",(i<<12) | l1,
+ pt[i]&0xFFFFF000);
+ eprintf("l2pt[0x%x]=0x%x ",i, pt[i]);
+ eprintf("s=%u ", (pt[i]>>10) &0x1);
+ eprintf("apx=%u ", (pt[i]>> 9) &0x1);
+ eprintf("tex=%u ", (pt[i]>> 6) &0x7);
+ eprintf("ap=%u ", (pt[i]>> 4) &0x3);
+ eprintf("c=%u ", (pt[i]>> 3) &0x1);
+ eprintf("b=%u\n", (pt[i]>> 2) &0x1);
+ break;
+ }
+ }
+}
+
+void
+dump_l1pagetable(uint32_t pta)
+{
+ int i;
+ eprintf("L1 pagetable starts at 0x%x\n",pta);
+ volatile uint32_t *pt = (volatile uint32_t*)pta;
+ for (i=0; i<4096;i++) {
+ switch (pt[i] & 0x3) {
+ case 1:
+ eprintf("0x%x -> L2 ",i<<20);
+ eprintf("l1pt[0x%x]=0x%x ",i, pt[i]);
+ eprintf("l2desc=0x%x ",pt[i] & 0xFFFFFC00);
+ eprintf("p=%u ",(pt[i]>>9) &0x1);
+ eprintf("domain=0x%x\n",(pt[i]>>5) &0xF);
+ dump_l2pagetable(pt[i] & 0xFFFFFC00, i<<20);
+ break;
+ case 2:
+ if (pt[i] &0x40000) {
+ eprintf("0x%x -> 0x%x 16M ",i<<20, pt[i] & 0xFF000000);
+ eprintf("l1pt[0x%x]=0x%x ",i, pt[i]);
+ eprintf("base=0x%x ", ((pt[i]>>24)));
+ } else {
+ eprintf("0x%x -> 0x%x 1M ",i<<20, pt[i] & 0xFFF00000);
+ eprintf("l1pt[0x%x]=0x%x ",i, pt[i]);
+ eprintf("base=0x%x ", (pt[i]>>20));
+ }
+ eprintf("nG=%u ", (pt[i]>>17) &0x1);
+ eprintf("s=%u ", (pt[i]>>16) &0x1);
+ eprintf("apx=%u ", (pt[i]>>15) &0x1);
+ eprintf("tex=%u ", (pt[i]>>12) &0x7);
+ eprintf("ap=%u ", (pt[i]>>10) &0x3);
+ eprintf("p=%u ", (pt[i]>> 9) &0x1);
+ eprintf("domain=0x%x ", (pt[i]>> 5) &0xF);
+ eprintf("xn=%u ", (pt[i]>> 4) &0x1);
+ eprintf("c=%u ", (pt[i]>> 3) &0x1);
+ eprintf("b=%u\n", (pt[i]>> 2) &0x1);
+ break;
+ case 3:
+ eprintf("pt[0x%x] 0x%x RESV\n",i, pt[i]);
+ break;
+ }
+ }
+}
Added: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.h Thu Jun 7 15:32:54 2012 (r237265)
@@ -0,0 +1,45 @@
+/*-
+ * Copyright (c) 2009 Guillaume Ballet
+ * Copyright (c) 2012 Aleksander Dutkowski
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef AM37X_EARLY_UART_INC
+#define AM37X_EARLY_UART_INC
+
+void
+arm_early_putc( char c );
+
+void
+arm_early_puts(unsigned char *str);
+
+void
+eprintf(const char *fmt,...);
+
+void
+dump_l1pagetable(uint32_t pta);
+
+void
+dump_l2pagetable(uint32_t pta, uint32_t l1);
+#endif /* ----- #ifndef AM37X_EARLY_UART_INC ----- */
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/files.am37x
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/files.am37x Thu Jun 7 15:08:05 2012 (r237264)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/files.am37x Thu Jun 7 15:32:54 2012 (r237265)
@@ -1,9 +1,10 @@
#$FreeBSD$
-arm/ti/aintc.c standard
-arm/ti/am37x/am37x_prcm.c standard
+arm/ti/aintc.c standard
+arm/ti/am37x/am37x_prcm.c standard
arm/ti/am37x/am37x_dmtimer.c standard
arm/ti/am37x/am37x_scm_padconf.c standard
-arm/ti/ti_edma3.c standard
-arm/ti/ti_mmchs.c optional mmc
-arm/ti/cpsw/if_cpsw.c optional cpsw
+arm/ti/ti_edma3.c standard
+arm/ti/ti_mmchs.c optional mmc
+arm/ti/cpsw/if_cpsw.c optional cpsw
+arm/ti/am37x/am37x_early_uart.c standard
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c Thu Jun 7 15:08:05 2012 (r237264)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c Thu Jun 7 15:32:54 2012 (r237265)
@@ -89,6 +89,7 @@
#include <sys/reboot.h>
#include <arm/ti/omap4/omap4_reg.h>
+#include <arm/ti/am37x/am37x_early_uart.h>
#define DEBUG
#ifdef DEBUG
@@ -334,8 +335,7 @@
u_int l1pagetable;
int i = 0, j = 0;
-
- beagle_early_puts( "BeagleBoard-XM revC FreeBSD hababababa booting...\n" );
+ arm_early_puts( "BeagleBoard-XM revC FreeBSD hababababa booting...\n" );
kmdp = NULL;
lastaddr = 0;
@@ -343,9 +343,9 @@
dtbp = (vm_offset_t)NULL;
- beagle_early_puts( "set_cpufuncs()..." );
+ arm_early_puts( "set_cpufuncs()..." );
set_cpufuncs();
- beagle_early_puts( "done!\n" );
+ arm_early_puts( "done!\n" );
/*
* Mask metadata pointer: it is supposed to be on page boundary. If
@@ -353,7 +353,7 @@
* bootloader must have passed us something else than the metadata
* ptr... In this case we want to fall back to some built-in settings.
*/
- beagle_early_puts( "FDT related stuff..." );
+ arm_early_puts( "FDT related stuff..." );
mdp = (void *)((uint32_t)mdp & ~PAGE_MASK);
/* Parse metadata and fetch parameters */
@@ -398,16 +398,18 @@
&memsize) != 0)
while(1);
+ eprintf( "Memory size: %d\n", memsize );
+
// if (fdt_immr_addr(OMAP44XX_L4_PERIPH_VBASE) != 0)
// while (1);
- beagle_early_puts( "done!\n" );
+ arm_early_puts( "done!\n" );
/* Platform-specific initialisation */
pmap_bootstrap_lastaddr = DEVMAP_BOOTSTRAP_MAP_START - ARM_NOCACHE_KVA_SIZE;
- beagle_early_puts( "pcpu0_init()..." );
+ arm_early_puts( "pcpu0_init()..." );
pcpu0_init();
- beagle_early_puts( "done!\n" );
+ arm_early_puts( "done!\n" );
/* Calculate number of L2 tables needed for mapping vm_page_array */
l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page);
@@ -425,7 +427,7 @@
#define KERNEL_TEXT_BASE (KERNBASE)
freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
- beagle_early_puts( "allocing pages..." );
+ arm_early_puts( "allocing pages..." );
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_va, (np)); \
@@ -474,8 +476,8 @@
init_param1();
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
- beagle_early_puts( "done!\n" );
- beagle_early_puts( "pmapping pages..." );
+ arm_early_puts( "done!\n" );
+ arm_early_puts( "pmapping pages..." );
/*
* Now we start construction of the L1 page table
@@ -513,7 +515,6 @@
kernel_pt_table[0].pv_pa,
L2_TABLE_SIZE_REAL * l2size,
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
- beagle_early_puts( "done!\n" );
/* Map allocated DPCPU, stacks and msgbuf */
pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa,
@@ -525,30 +526,33 @@
&kernel_pt_table[l2size - 1]);
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE);
- beagle_early_puts( "done!\n" );
/* Map pmap_devmap[] entries */
if (platform_devmap_init() != 0)
while (1);
- beagle_early_puts( "done!\n" );
- beagle_early_puts( "pmap_devmap_bootstrap()..." );
+ arm_early_puts( "done!\n" );
+ arm_early_puts( "pmap_devmap_bootstrap()..." );
pmap_devmap_bootstrap(l1pagetable, pmap_devmap_bootstrap_table);
- beagle_early_puts( "done!\n" );
+ arm_early_puts( "done!\n" );
- beagle_early_puts( "cpu_domains()..." );
+ arm_early_puts( "cpu_domains()..." );
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
DOMAIN_CLIENT);
- beagle_early_puts( "done!\n" );
+ arm_early_puts( "done!\n" );
pmap_pa = kernel_l1pt.pv_pa;
- beagle_early_puts( "settb()..." );
+
+ arm_early_puts( "Dumping memory layout!\n" );
+ dump_l1pagetable( kernel_l1pt.pv_pa );
+
+ arm_early_puts( "setttb()..." );
setttb(kernel_l1pt.pv_pa);
- beagle_early_puts( "done!\n" );
- beagle_early_puts( "cpu_tlb_flushID()..." );
+ arm_early_puts( "done!\n" );
+ arm_early_puts( "cpu_tlb_flushID()..." );
cpu_tlb_flushID();
- beagle_early_puts( "done!\n" );
- beagle_early_puts( "cpu_domains2()..." );
+ arm_early_puts( "done!\n" );
+ arm_early_puts( "cpu_domains2()..." );
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
- beagle_early_puts( "done!\n" );
+ arm_early_puts( "done!\n" );
/*
* Only after the SOC registers block is mapped we can perform device
@@ -643,7 +647,7 @@
undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
}
-#define FDT_DEVMAP_MAX (2) // FIXME
+#define FDT_DEVMAP_MAX (3) // FIXME
static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = {
{ 0, 0, 0, 0, 0, }
};
@@ -677,6 +681,12 @@
fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
fdt_devmap[i].pd_cache = PTE_DEVICE;
i++;
+ fdt_devmap[i].pd_va = 0xE9000000;
+ fdt_devmap[i].pd_pa = 0x49000000;
+ fdt_devmap[i].pd_size = 0x100000;
+ fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
+ fdt_devmap[i].pd_cache = PTE_DEVICE;
+ i++;
#else
#error "Unknown SoC"
#endif
Modified: soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Thu Jun 7 15:08:05 2012 (r237264)
+++ soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Thu Jun 7 15:32:54 2012 (r237265)
@@ -27,8 +27,8 @@
/dts-v1/;
/ {
- model = "beaglebone";
- compatible = "beaglebone", "ti,am335x";
+ model = "beagleboardxm";
+ compatible = "beagleboard", "ti,am37x";
#address-cells = <1>;
#size-cells = <1>;
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