svn commit: r490609 - in head/cad: . verilator

[Steve Wills]

Author: swills
Date: Thu Jan 17 23:27:11 2019
New Revision: 490609
URL: https://svnweb.freebsd.org/changeset/ports/490609

Log:
  cad/verilator: create port
  
  Verilator is the fastest free Verilog HDL simulator, and beats most commercial
  simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
  PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
  designed for large projects where fast simulation performance is of primary
  concern, and is especially well suited to generate executable models of CPUs
  for embedded software design teams.
  
  WWW: https://www.veripool.org/projects/verilator/wiki/Intro
  
  PR:		230761
  Submitted by:	Kevin Zheng <kevinz5000 at gmail.com>

Added:
  head/cad/verilator/
  head/cad/verilator/Makefile   (contents, props changed)
  head/cad/verilator/distinfo   (contents, props changed)
  head/cad/verilator/pkg-descr   (contents, props changed)
  head/cad/verilator/pkg-plist   (contents, props changed)
Modified:
  head/cad/Makefile   (contents, props changed)

Modified: head/cad/Makefile
==============================================================================
--- head/cad/Makefile	Thu Jan 17 23:24:49 2019	(r490608)
+++ head/cad/Makefile	Thu Jan 17 23:27:11 2019	(r490609)
@@ -101,6 +101,7 @@
     SUBDIR += tochnog
     SUBDIR += transcalc
     SUBDIR += varkon
+    SUBDIR += verilator
     SUBDIR += verilog-mode.el
     SUBDIR += xcircuit
     SUBDIR += xtrkcad

Added: head/cad/verilator/Makefile
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/cad/verilator/Makefile	Thu Jan 17 23:27:11 2019	(r490609)
@@ -0,0 +1,31 @@
+# $FreeBSD$
+
+PORTNAME=	verilator
+PORTVERSION=	3.924
+CATEGORIES=	cad
+MASTER_SITES=	https://www.veripool.org/ftp/
+
+MAINTAINER=	kevinz5000 at gmail.com
+COMMENT=	Synthesizable Verilog to C++ compiler
+
+LICENSE=	GPLv3
+LICENSE_FILE=	${WRKSRC}/COPYING
+
+BUILD_DEPENDS=	flex:textproc/flex
+
+USES=		bison gmake pathfix perl5 tar:tgz
+
+GNU_CONFIGURE=	yes
+CONFIGURE_ENV=	INSTALL_PROGRAM="${INSTALL_SCRIPT}"
+
+post-patch:
+	${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
+	    ${WRKSRC}/Makefile.in
+
+post-build:
+	@${STRIP_CMD} ${WRKSRC}/bin/verilator_bin
+
+post-install:
+	${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg
+
+.include <bsd.port.mk>

Added: head/cad/verilator/distinfo
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/cad/verilator/distinfo	Thu Jan 17 23:27:11 2019	(r490609)
@@ -0,0 +1,3 @@
+TIMESTAMP = 1534354040
+SHA256 (verilator-3.924.tgz) = 7dcb19711b8630ada59f0d3d7409faa9649e37bf4c53a0bbfcad32afb28b5975
+SIZE (verilator-3.924.tgz) = 2163952

Added: head/cad/verilator/pkg-descr
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/cad/verilator/pkg-descr	Thu Jan 17 23:27:11 2019	(r490609)
@@ -0,0 +1,8 @@
+Verilator is the fastest free Verilog HDL simulator, and beats most commercial
+simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
+PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
+designed for large projects where fast simulation performance is of primary
+concern, and is especially well suited to generate executable models of CPUs
+for embedded software design teams.
+
+WWW: https://www.veripool.org/projects/verilator/wiki/Intro

Added: head/cad/verilator/pkg-plist
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/cad/verilator/pkg-plist	Thu Jan 17 23:27:11 2019	(r490609)
@@ -0,0 +1,54 @@
+bin/verilator
+bin/verilator_bin
+bin/verilator_coverage
+bin/verilator_profcfunc
+libdata/pkgconfig/verilator.pc
+man/man1/verilator.1.gz
+man/man1/verilator_coverage.1.gz
+man/man1/verilator_profcfunc.1.gz
+%%DATADIR%%/bin/verilator_includer
+%%DATADIR%%/examples/hello_world_c/Makefile
+%%DATADIR%%/examples/hello_world_c/sim_main.cpp
+%%DATADIR%%/examples/hello_world_c/top.v
+%%DATADIR%%/examples/hello_world_sc/Makefile
+%%DATADIR%%/examples/hello_world_sc/sc_main.cpp
+%%DATADIR%%/examples/hello_world_sc/top.v
+%%DATADIR%%/examples/tracing_c/Makefile
+%%DATADIR%%/examples/tracing_c/Makefile_obj
+%%DATADIR%%/examples/tracing_c/input.vc
+%%DATADIR%%/examples/tracing_c/sim_main.cpp
+%%DATADIR%%/examples/tracing_c/sub.v
+%%DATADIR%%/examples/tracing_c/top.v
+%%DATADIR%%/examples/tracing_sc/Makefile
+%%DATADIR%%/examples/tracing_sc/Makefile_obj
+%%DATADIR%%/examples/tracing_sc/input.vc
+%%DATADIR%%/examples/tracing_sc/sc_main.cpp
+%%DATADIR%%/examples/tracing_sc/sub.v
+%%DATADIR%%/examples/tracing_sc/top.v
+%%DATADIR%%/include/verilated.cpp
+%%DATADIR%%/include/verilated.h
+%%DATADIR%%/include/verilated.mk
+%%DATADIR%%/include/verilated.v
+%%DATADIR%%/include/verilated_config.h
+%%DATADIR%%/include/verilated_config.h.in
+%%DATADIR%%/include/verilated_cov.cpp
+%%DATADIR%%/include/verilated_cov.h
+%%DATADIR%%/include/verilated_cov_key.h
+%%DATADIR%%/include/verilated_dpi.cpp
+%%DATADIR%%/include/verilated_dpi.h
+%%DATADIR%%/include/verilated_heavy.h
+%%DATADIR%%/include/verilated_imp.h
+%%DATADIR%%/include/verilated_save.cpp
+%%DATADIR%%/include/verilated_save.h
+%%DATADIR%%/include/verilated_sc.h
+%%DATADIR%%/include/verilated_sym_props.h
+%%DATADIR%%/include/verilated_syms.h
+%%DATADIR%%/include/verilated_vcd_c.cpp
+%%DATADIR%%/include/verilated_vcd_c.h
+%%DATADIR%%/include/verilated_vcd_sc.cpp
+%%DATADIR%%/include/verilated_vcd_sc.h
+%%DATADIR%%/include/verilated_vpi.cpp
+%%DATADIR%%/include/verilated_vpi.h
+%%DATADIR%%/include/verilatedos.h
+%%DATADIR%%/include/vltstd/svdpi.h
+%%DATADIR%%/include/vltstd/vpi_user.h