svn commit: r491344 - head/cad/verilator

[Steve Wills]

Author: swills
Date: Sun Jan 27 12:34:34 2019
New Revision: 491344
URL: https://svnweb.freebsd.org/changeset/ports/491344

Log:
  cad/verilator: remove unnecessary BUILD_DEPENDS
  
  PR:		235053
  Submitted by:	John Hein <jcfyecrayz at liamekaens.com>
  Approved by:	Kevin Zheng <kevinz5000 at gmail.com> (maintainer)

Modified:
  head/cad/verilator/Makefile   (contents, props changed)

Modified: head/cad/verilator/Makefile
==============================================================================
--- head/cad/verilator/Makefile	Sun Jan 27 12:25:31 2019	(r491343)
+++ head/cad/verilator/Makefile	Sun Jan 27 12:34:34 2019	(r491344)
@@ -2,6 +2,7 @@
 
 PORTNAME=	verilator
 PORTVERSION=	4.008
+PORTREVISION=	1
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
@@ -10,8 +11,6 @@ COMMENT=	Synthesizable Verilog to C++ compiler
 
 LICENSE=	GPLv3
 LICENSE_FILE=	${WRKSRC}/COPYING
-
-BUILD_DEPENDS=	flex:textproc/flex
 
 USES=		bison gmake pathfix perl5 tar:tgz