svn commit: r471848 - in head/devel: . lattice-ice40-tools
Tobias Kortkamp
tobik at FreeBSD.org
Wed Jun 6 14:52:59 UTC 2018
Author: tobik
Date: Wed Jun 6 14:52:57 2018
New Revision: 471848
URL: https://svnweb.freebsd.org/changeset/ports/471848
Log:
New port: devel/lattice-ice40-tools
Metaport which enables a fully open source Verilog-to-Bitstream
flow for iCE40 FPGAs.
WWW: http://www.clifford.at/icestorm
PR: 227592
Submitted by: Johnny Sorocil <jsorocil at gmail.com>
Differential Revision: https://reviews.freebsd.org/D15632
Added:
head/devel/lattice-ice40-tools/
head/devel/lattice-ice40-tools/Makefile (contents, props changed)
head/devel/lattice-ice40-tools/distinfo (contents, props changed)
head/devel/lattice-ice40-tools/pkg-descr (contents, props changed)
Modified:
head/devel/Makefile
Modified: head/devel/Makefile
==============================================================================
--- head/devel/Makefile Wed Jun 6 14:42:58 2018 (r471847)
+++ head/devel/Makefile Wed Jun 6 14:52:57 2018 (r471848)
@@ -1329,6 +1329,7 @@
SUBDIR += lasi
SUBDIR += lattice-ice40-examples-hx1k
SUBDIR += lattice-ice40-examples-hx8k
+ SUBDIR += lattice-ice40-tools
SUBDIR += lcov
SUBDIR += leaktracer
SUBDIR += leatherman
Added: head/devel/lattice-ice40-tools/Makefile
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/lattice-ice40-tools/Makefile Wed Jun 6 14:52:57 2018 (r471848)
@@ -0,0 +1,25 @@
+# Created by: Johnny Sorocil <jsorocil at gmail.com>
+# $FreeBSD$
+
+PORTNAME= lattice-ice40-tools
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= jsorocil at gmail.com
+COMMENT= Open source tools for Lattice iCE40 FPGAs
+
+RUN_DEPENDS= abc:cad/abc \
+ arachne-pnr:devel/arachne-pnr \
+ icepack:devel/icestorm \
+ yosys:devel/yosys
+
+USES= metaport
+
+OPTIONS_DEFINE= EXAMPLES
+
+EXAMPLES_DESC= Build examples for Olimex iCE40 FPGA boards
+
+EXAMPLES_RUN_DEPENDS= lattice-ice40-examples-hx1k>=g0:devel/lattice-ice40-examples-hx1k \
+ lattice-ice40-examples-hx8k>=g0:devel/lattice-ice40-examples-hx8k
+
+.include <bsd.port.mk>
Added: head/devel/lattice-ice40-tools/distinfo
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/lattice-ice40-tools/distinfo Wed Jun 6 14:52:57 2018 (r471848)
@@ -0,0 +1,5 @@
+TIMESTAMP = 1528041379
+SHA256 (OLIMEX-iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz) = 99a6328ccfcd7a6a8a25d1521c028d1a1b5418b7de1dcc3b2db40e7d1bed9034
+SIZE (OLIMEX-iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz) = 2181827
+SHA256 (OLIMEX-iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz) = 1f6d29d1420f608fda49f1b50085453bd4c6d32067773d210af386f95b24bd3a
+SIZE (OLIMEX-iCE40HX8K-EVB-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz) = 1370726
Added: head/devel/lattice-ice40-tools/pkg-descr
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/lattice-ice40-tools/pkg-descr Wed Jun 6 14:52:57 2018 (r471848)
@@ -0,0 +1,4 @@
+Metaport which enables a fully open source Verilog-to-Bitstream
+flow for iCE40 FPGAs.
+
+WWW: http://www.clifford.at/icestorm
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