svn commit: r471844 - in head/devel: . yosys
Tobias Kortkamp
tobik at FreeBSD.org
Wed Jun 6 14:19:53 UTC 2018
Author: tobik
Date: Wed Jun 6 14:19:51 2018
New Revision: 471844
URL: https://svnweb.freebsd.org/changeset/ports/471844
Log:
New port: devel/yosys
Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.
WWW: http://www.clifford.at/yosys/
PR: 227591
Submitted by: Johnny Sorocil <jsorocil at gmail.com>
Differential Revision: https://reviews.freebsd.org/D15632
Added:
head/devel/yosys/
head/devel/yosys/Makefile (contents, props changed)
head/devel/yosys/distinfo (contents, props changed)
head/devel/yosys/pkg-descr (contents, props changed)
head/devel/yosys/pkg-plist (contents, props changed)
Modified:
head/devel/Makefile
Modified: head/devel/Makefile
==============================================================================
--- head/devel/Makefile Wed Jun 6 13:53:04 2018 (r471843)
+++ head/devel/Makefile Wed Jun 6 14:19:51 2018 (r471844)
@@ -6246,6 +6246,7 @@
SUBDIR += yaml2argdata
SUBDIR += yasm
SUBDIR += yasm-devel
+ SUBDIR += yosys
SUBDIR += youcompleteme
SUBDIR += z80-asm
SUBDIR += z80asm
Added: head/devel/yosys/Makefile
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/yosys/Makefile Wed Jun 6 14:19:51 2018 (r471844)
@@ -0,0 +1,34 @@
+# Created by: Johnny Sorocil <jsorocil at gmail.com>
+# $FreeBSD$
+
+PORTNAME= yosys
+DISTVERSION= 0.7-783
+DISTVERSIONSUFFIX= -gbab39eac
+CATEGORIES= devel
+
+MAINTAINER= jsorocil at gmail.com
+COMMENT= Yosys Open SYnthesis Suite
+
+LICENSE= ISCL
+LICENSE_FILE= ${WRKSRC}/COPYING
+
+BUILD_DEPENDS= abc:cad/abc \
+ bash:shells/bash \
+ gawk:lang/gawk
+LIB_DEPENDS= libffi.so:devel/libffi
+
+USES= bison gmake pkgconfig python:3.6+ readline shebangfix tcl
+SHEBANG_FILES= backends/smt2/smtbmc.py \
+ misc/yosys-config.in
+
+USE_GITHUB= yes
+GH_ACCOUNT= YosysHQ
+GH_TAGNAME= bab39eacce5c17c42d50a3a60a67cc8a9ee52d98
+
+BINARY_ALIAS= python3=${PYTHON_CMD} tclsh=${TCLSH}
+MAKE_ARGS= ABCEXTERNAL=abc
+
+post-install:
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys
+
+.include <bsd.port.mk>
Added: head/devel/yosys/distinfo
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/yosys/distinfo Wed Jun 6 14:19:51 2018 (r471844)
@@ -0,0 +1,3 @@
+TIMESTAMP = 1527191683
+SHA256 (YosysHQ-yosys-0.7-783-gbab39eac-bab39eacce5c17c42d50a3a60a67cc8a9ee52d98_GH0.tar.gz) = 1c97050a19f653fc957550cb5a505e1ebcb5722eade487bd86e8a5f9681ae09c
+SIZE (YosysHQ-yosys-0.7-783-gbab39eac-bab39eacce5c17c42d50a3a60a67cc8a9ee52d98_GH0.tar.gz) = 1089933
Added: head/devel/yosys/pkg-descr
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/yosys/pkg-descr Wed Jun 6 14:19:51 2018 (r471844)
@@ -0,0 +1,5 @@
+Yosys is a framework for Verilog RTL synthesis. It currently has
+extensive Verilog-2005 support and provides a basic set of synthesis
+algorithms for various application domains.
+
+WWW: http://www.clifford.at/yosys/
Added: head/devel/yosys/pkg-plist
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/devel/yosys/pkg-plist Wed Jun 6 14:19:51 2018 (r471844)
@@ -0,0 +1,86 @@
+bin/yosys
+bin/yosys-config
+bin/yosys-filterlib
+bin/yosys-smtbmc
+%%DATADIR%%/achronix/speedster22i/cells_map.v
+%%DATADIR%%/achronix/speedster22i/cells_sim.v
+%%DATADIR%%/adff2dff.v
+%%DATADIR%%/cells.lib
+%%DATADIR%%/coolrunner2/cells_latch.v
+%%DATADIR%%/coolrunner2/cells_sim.v
+%%DATADIR%%/coolrunner2/tff_extract.v
+%%DATADIR%%/coolrunner2/xc2_dff.lib
+%%DATADIR%%/dff2ff.v
+%%DATADIR%%/gowin/cells_map.v
+%%DATADIR%%/gowin/cells_sim.v
+%%DATADIR%%/greenpak4/cells_blackbox.v
+%%DATADIR%%/greenpak4/cells_latch.v
+%%DATADIR%%/greenpak4/cells_map.v
+%%DATADIR%%/greenpak4/cells_sim_ams.v
+%%DATADIR%%/greenpak4/cells_sim_digital.v
+%%DATADIR%%/greenpak4/cells_sim_wip.v
+%%DATADIR%%/greenpak4/cells_sim.v
+%%DATADIR%%/greenpak4/gp_dff.lib
+%%DATADIR%%/ice40/arith_map.v
+%%DATADIR%%/ice40/brams_init1.vh
+%%DATADIR%%/ice40/brams_init2.vh
+%%DATADIR%%/ice40/brams_init3.vh
+%%DATADIR%%/ice40/brams_map.v
+%%DATADIR%%/ice40/brams.txt
+%%DATADIR%%/ice40/cells_map.v
+%%DATADIR%%/ice40/cells_sim.v
+%%DATADIR%%/ice40/latches_map.v
+%%DATADIR%%/include/backends/ilang/ilang_backend.h
+%%DATADIR%%/include/frontends/ast/ast.h
+%%DATADIR%%/include/kernel/celledges.h
+%%DATADIR%%/include/kernel/celltypes.h
+%%DATADIR%%/include/kernel/consteval.h
+%%DATADIR%%/include/kernel/hashlib.h
+%%DATADIR%%/include/kernel/log.h
+%%DATADIR%%/include/kernel/macc.h
+%%DATADIR%%/include/kernel/modtools.h
+%%DATADIR%%/include/kernel/register.h
+%%DATADIR%%/include/kernel/rtlil.h
+%%DATADIR%%/include/kernel/satgen.h
+%%DATADIR%%/include/kernel/sigtools.h
+%%DATADIR%%/include/kernel/utils.h
+%%DATADIR%%/include/kernel/yosys.h
+%%DATADIR%%/include/libs/ezsat/ezminisat.h
+%%DATADIR%%/include/libs/ezsat/ezsat.h
+%%DATADIR%%/include/libs/sha1/sha1.h
+%%DATADIR%%/include/passes/fsm/fsmdata.h
+%%DATADIR%%/intel/a10gx/cells_map.v
+%%DATADIR%%/intel/a10gx/cells_sim.v
+%%DATADIR%%/intel/common/altpll_bb.v
+%%DATADIR%%/intel/common/brams_map.v
+%%DATADIR%%/intel/common/brams.txt
+%%DATADIR%%/intel/common/m9k_bb.v
+%%DATADIR%%/intel/cyclone10/cells_map.v
+%%DATADIR%%/intel/cyclone10/cells_sim.v
+%%DATADIR%%/intel/cycloneiv/cells_map.v
+%%DATADIR%%/intel/cycloneiv/cells_sim.v
+%%DATADIR%%/intel/cycloneive/cells_map.v
+%%DATADIR%%/intel/cycloneive/cells_sim.v
+%%DATADIR%%/intel/cyclonev/cells_map.v
+%%DATADIR%%/intel/cyclonev/cells_sim.v
+%%DATADIR%%/intel/max10/cells_map.v
+%%DATADIR%%/intel/max10/cells_sim.v
+%%DATADIR%%/pmux2mux.v
+%%DATADIR%%/python3/smtio.py
+%%DATADIR%%/simcells.v
+%%DATADIR%%/simlib.v
+%%DATADIR%%/techmap.v
+%%DATADIR%%/xilinx/arith_map.v
+%%DATADIR%%/xilinx/brams_bb.v
+%%DATADIR%%/xilinx/brams_init_%%PYTHON_SUFFIX%%.vh
+%%DATADIR%%/xilinx/brams_init_16.vh
+%%DATADIR%%/xilinx/brams_init_18.vh
+%%DATADIR%%/xilinx/brams_init_32.vh
+%%DATADIR%%/xilinx/brams_map.v
+%%DATADIR%%/xilinx/brams.txt
+%%DATADIR%%/xilinx/cells_map.v
+%%DATADIR%%/xilinx/cells_sim.v
+%%DATADIR%%/xilinx/cells_xtra.v
+%%DATADIR%%/xilinx/drams_map.v
+%%DATADIR%%/xilinx/drams.txt
+%%DATADIR%%/xilinx/lut2lut.v
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