PERFORCE change 222839 for review

[Brooks Davis]

http://p4web.freebsd.org/@@222839?ac=10

Change 222839 by brooks at brooks_zenith on 2013/03/13 20:37:52

	Move the majority of the partitioning of the Intel StrataFlash into
	FDT.  This allows us to store hardware or bitcode defined
	offsets in the FDT which will eventually live in a ROM on the
	FPGA.
	
	Retain the /dev/map/fpga and /dev/map/kernel maps for compatiblity
	for now.
	
	Remove references to isf[01].

Affected files ...

.. //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beripad-de4.dts#18 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/conf/BERI_DE4.hints#25 edit

Differences ...

==== //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beripad-de4.dts#18 (text+ko) ====

@@ -1,5 +1,6 @@
 /*-
  * Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
  * All rights reserved.
  *
  * This software was developed by SRI International and the University of
@@ -100,8 +101,40 @@
 		 * Ethernet addresses for now.
 		 */
 		flash at 74000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
 			compatible = "cfi-flash";
 			reg = <0x74000000 0x4000000>;
+
+			/* Board configuration */
+			partition at 0 {
+				reg = <0x0 0x20000>;
+				label = "config";
+			};
+
+			/* Power up FPGA image */
+			partition at 20000 {
+				reg = <0x20000 0xc00000>;
+				label = "fpga0";
+			};
+
+			/* Secondary FPGA image (on RE_CONFIGn button) */
+			partition at C20000 {
+				reg = <0xc20000 0xc00000>;
+				label = "fpga1";
+			};
+
+			/* Space for operating system use */
+			partition at 1820000 {
+				reg = <0x1820000 0x027c0000>;
+				label = "os";
+			};
+
+			/* Second stage bootloader */
+			parition at 3fe0000 {
+				reg = <0x3fe0000 0x20000>;
+				label = "boot";
+			};
 		};
 
 		ethernet at 7f007000 {

==== //depot/projects/ctsrd/beribsd/src/sys/mips/conf/BERI_DE4.hints#25 (text+ko) ====

@@ -1,67 +1,16 @@
 # $FreeBSD: head/sys/mips/conf/BERI_DE4.hints 239713 2012-08-26 10:40:13Z rwatson $
 
-# Reserved configuration blocks.  Don't touch.
-hint.map.0.at="cfid0"
+# Hardwired location of bitfile
+hint.map.0.at="cfid0s.fpga0"
 hint.map.0.start=0x00000000
-hint.map.0.end=0x00020000
-hint.map.0.name="config"
-hint.map.0.readonly=1
-
-# Hardwired location of bitfile
-hint.map.1.at="cfid0"
-hint.map.1.start=0x00020000
-hint.map.1.end=0x01820000
-hint.map.1.name="fpga"
-
-# Currently unused space on the first chip
-# XXX: To be merged with the kernel map when we begin using the boot loader
-hint.map.2.at="cfid0"
-hint.map.2.start=0x01820000
-hint.map.2.end=0x02000000
-hint.map.2.name="reserved"
+hint.map.0.end=0x00c00000
+hint.map.0.name="fpga"
 
 # Kernel on the second chip
-hint.map.3.at="cfid0"
-hint.map.3.start=0x02000000
-hint.map.3.end=0x03fe0000
-hint.map.3.name="kernel"
-
-# Area for use by the boot loader
-hint.map.4.at="cfid0"
-hint.map.4.start=0x03fe0000
-hint.map.4.end=0x04000000
-hint.map.4.name="boot"
-
-# Reserved configuration blocks.  Don't touch.
-hint.map.5.at="isf0"
-hint.map.5.start=0x00000000
-hint.map.5.end=0x00020000
-hint.map.5.name="config"
-hint.map.5.readonly=1
-
-# Hardwired location of bitfile
-hint.map.6.at="isf0"
-hint.map.6.start=0x00020000
-hint.map.6.end=0x01820000
-hint.map.6.name="fpga"
-
-# Currently unused space on the first chip
-hint.map.7.at="isf0"
-hint.map.7.start=0x01820000
-hint.map.7.end=0x02000000
-hint.map.7.name="reserved"
-
-# Kernel on the second chip
-hint.map.8.at="isf1"
-hint.map.8.start=0x00000000
-hint.map.8.end=0x01fe0000
-hint.map.8.name="kernel"
-
-# Area for use by the boot loader
-hint.map.10.at="isf1"
-hint.map.10.start=0x01fe0000
-hint.map.10.end=0x02000000
-hint.map.10.name="kernel"
+hint.map.1.at="cfid0s.os"
+hint.map.1.start=0x007e0000
+hint.map.1.end=0x01fe0000
+hint.map.1.name="kernel"
 
 # Altera Triple-Speed Ethernet Mac, present in tPad and DE-4 configurations
 # configured from fdt(4) but PHYs are still described in here.