PERFORCE change 230524 for review

[Brooks Davis]

http://p4web.freebsd.org/@@230524?ac=10

Change 230524 by brooks at brooks_zenith on 2013/07/03 22:33:14

	Introduce a platform_init_secondary() function for MIPS
	platforms that is called from init_secondary() after the BSP
	wakes each AP, but before they indicate they are done
	initalizing.  Use this to differ PIC setup until after beripic
	has been probed.  With this change BERI2 make it to single user
	in simulation.

Affected files ...

.. //depot/projects/ctsrd/beribsd/src/sys/mips/beri/beri_mp.c#3 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/cavium/octeon_mp.c#4 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/gxemul/gxemul_machdep.c#6 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/include/hwfunc.h#5 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/mp_machdep.c#4 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/nlm/xlp_machdep.c#4 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/rmi/xlr_machdep.c#4 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/sibyte/sb_machdep.c#5 edit

Differences ...

==== //depot/projects/ctsrd/beribsd/src/sys/mips/beri/beri_mp.c#3 (text+ko) ====

@@ -95,6 +95,25 @@
 }
 
 void
+platform_init_secondary(int cpuid)
+{
+	device_t ic;
+	int ipi;
+
+	ipi = platform_ipi_intrnum();
+
+	/* XXX: single core/pic */
+	ic = SLIST_FIRST(&fdt_ic_list_head)->dev;
+	FDT_IC_SETUP_IPI(ic, cpuid, ipi);
+	picmap[cpuid] = ic;
+
+	/* Unmask the interrupt */
+	if (cpuid != 0)
+		mips_wr_status(mips_rd_status() | (((1 << ipi) << 8) << 2));
+}
+
+
+void
 platform_ipi_send(int cpuid)
 {
 
@@ -135,7 +154,6 @@
 platform_init_ap(int cpuid)
 {
 	u_int clock_int_mask;
-	device_t ic;
 
 	KASSERT(cpuid < MAXCPU, ("%s: invalid CPU id %d", __func__, cpuid));
 
@@ -144,14 +162,6 @@
 	 */
 	clock_int_mask = hard_int_mask(5);
 	set_intr_mask(clock_int_mask);
-
-	/*
-	 * Enable IPIs.
-	 */
-	/* XXX: single core/pic */
-	ic = SLIST_FIRST(&fdt_ic_list_head)->dev;
-	FDT_IC_SETUP_IPI(ic, cpuid, platform_ipi_intrnum());
-	picmap[cpuid] = ic;
 }
 
 /*
@@ -171,22 +181,31 @@
 	    ("%s: invalid CPU id %d", __func__, cpuid));
 	
 	cpu = cpu_of_nodes[cpuid];
-	if (OF_getprop(cpu, "status", &prop, sizeof(prop)) <= 0 &&
-	    OF_getprop(OF_parent(cpu), "status", &prop, sizeof(prop)))
-		panic("%s: CPU %d has no status property", __func__, cpuid);
-	else
-		if (strcmp("disabled", prop) != 0)
-			panic("%s: CPU %d status is '%s' not 'disabled'",
-			    __func__, cpuid, prop);
+	if (OF_getprop(cpu, "status", &prop, sizeof(prop)) <= 0) {
+		if (bootverbose)
+			printf("%s: CPU %d has no status property, "
+			    "trying parent\n", __func__, cpuid);
+		if (OF_getprop(OF_parent(cpu), "status", &prop,
+		    sizeof(prop)) <= 0)
+			panic("%s: CPU %d has no status property", __func__,
+			    cpuid);
+	}
+	if (strcmp("disabled", prop) != 0)
+		panic("%s: CPU %d status is '%s' not 'disabled'",
+		    __func__, cpuid, prop);
 	
-	if (OF_getprop(cpu, "enable-method", &prop, sizeof(prop)) <= 0 &&
-	    OF_getprop(OF_parent(cpu), "enable-method", &prop, sizeof(prop)))
-		panic("%s: CPU %d has no enable-method property", __func__,
-		    cpuid);
-	else
-		if (strcmp("spin-table", prop) != 0)
-			panic("%s: CPU %d enable-method is '%s' not "
-			    "'spin-table'", __func__, cpuid, prop);
+	if (OF_getprop(cpu, "enable-method", &prop, sizeof(prop)) <= 0) {
+		if (bootverbose)
+			printf("%s: CPU %d has no enable-method, "
+			    "trying parent\n", __func__, cpuid);
+		if (OF_getprop(OF_parent(cpu), "enable-method", &prop,
+		    sizeof(prop)) <= 0)
+			panic("%s: CPU %d has no enable-method property",
+			    __func__, cpuid);
+	}
+	if (strcmp("spin-table", prop) != 0)
+		panic("%s: CPU %d enable-method is '%s' not "
+		    "'spin-table'", __func__, cpuid, prop);
 
 	if (OF_getprop(cpu, "cpu-release-addr", &se, sizeof(se)) <= 0)
 		panic("%s: CPU %d has missing or invalid cpu-release-addr",

==== //depot/projects/ctsrd/beribsd/src/sys/mips/cavium/octeon_mp.c#4 (text+ko) ====

@@ -46,6 +46,12 @@
 unsigned octeon_ap_boot = ~0;
 
 void
+platform_init_secondary(int cpuid)
+{
+
+}
+
+void
 platform_ipi_send(int cpuid)
 {
 	cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);

==== //depot/projects/ctsrd/beribsd/src/sys/mips/gxemul/gxemul_machdep.c#6 (text+ko) ====

@@ -174,6 +174,12 @@
 
 #ifdef SMP
 void
+platform_init_secondary(int cpuid)
+{
+
+}
+
+void
 platform_ipi_send(int cpuid)
 {
 	GXEMUL_MP_DEV_WRITE(GXEMUL_MP_DEV_IPI_ONE, (1 << 16) | cpuid);

==== //depot/projects/ctsrd/beribsd/src/sys/mips/include/hwfunc.h#5 (text+ko) ====

@@ -70,6 +70,11 @@
 int platform_ipi_intrnum(void);
 
 /*
+ * Set up IPIs for this CPU.
+ */
+void platform_init_secondary(int cpuid);
+
+/*
  * Trigger a IPI interrupt on 'cpuid'.
  */
 void platform_ipi_send(int cpuid);

==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/mp_machdep.c#4 (text+ko) ====

@@ -301,6 +301,8 @@
 	while (!aps_ready)
 		;
 
+	platform_init_secondary(cpuid);
+
 	/* Initialize curthread. */
 	KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
 	PCPU_SET(curthread, PCPU_GET(idlethread));
@@ -342,6 +344,8 @@
 	if (mp_ncpus == 1)
 		return;
 
+	platform_init_secondary(0);
+
 	/*
 	 * IPI handler
 	 */

==== //depot/projects/ctsrd/beribsd/src/sys/mips/nlm/xlp_machdep.c#4 (text+ko) ====

@@ -697,6 +697,12 @@
 }
 
 void
+platform_init_secondary(int cpuid)
+{
+
+}
+
+void
 platform_ipi_send(int cpuid)
 {
 

==== //depot/projects/ctsrd/beribsd/src/sys/mips/rmi/xlr_machdep.c#4 (text+ko) ====

@@ -578,6 +578,12 @@
 }
 
 void
+platform_init_secondary(int cpuid)
+{
+
+}
+
+void
 platform_ipi_send(int cpuid)
 {
 

==== //depot/projects/ctsrd/beribsd/src/sys/mips/sibyte/sb_machdep.c#5 (text+ko) ====

@@ -295,6 +295,12 @@
 
 #ifdef SMP
 void
+platform_init_secondary(int cpuid)
+{
+
+}
+
+void
 platform_ipi_send(int cpuid)
 {
 	KASSERT(cpuid == 0 || cpuid == 1,