PERFORCE change 219757 for review
Robert Watson
rwatson at FreeBSD.org
Mon Nov 12 07:47:24 UTC 2012
http://p4web.freebsd.org/@@219757?ac=10
Change 219757 by rwatson at rwatson_zenith_cl_cam_ac_uk on 2012/11/12 07:47:16
Flesh out CHERI load via capability macros.
Affected files ...
.. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#14 edit
Differences ...
==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#14 (text+ko) ====
@@ -192,11 +192,41 @@
*
* XXXRW: immediates not yet supported by the assembler.
*/
+#define CHERI_CLB(rd, rt, offset, cb) do { \
+ __asm__ __volatile__ ("clb %0, %1($c%2)" : \
+ "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
+} while (0)
+
+#define CHERI_CLH(rd, rt, offset, cb) do { \
+ __asm__ __volatile__ ("clh %0, %1($c%2)" : \
+ "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
+} while (0)
+
#define CHERI_CLW(rd, rt, offset, cb) do { \
__asm__ __volatile__ ("clw %0, %1($c%2)" : \
"=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
} while (0)
+#define CHERI_CLD(rd, rt, offset, cb) do { \
+ __asm__ __volatile__ ("cld %0, %1($c%2)" : \
+ "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
+} while (0)
+
+#define CHERI_CLBU(rd, rt, offset, cb) do { \
+ __asm__ __volatile__ ("clbu %0, %1($c%2)" : \
+ "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
+} while (0)
+
+#define CHERI_CLHU(rd, rt, offset, cb) do { \
+ __asm__ __volatile__ ("clhu %0, %1($c%2)" : \
+ "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
+} while (0)
+
+#define CHERI_CLWU(rd, rt, offset, cb) do { \
+ __asm__ __volatile__ ("clwu %0, %1($c%2)" : \
+ "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \
+} while (0)
+
/*
* Routines that modify or replace values in capability registers, and that if
* if used on C0, require the compiler to write registers back to memory, and
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